upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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274 lines
7.6 KiB
274 lines
7.6 KiB
/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <common.h>
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#include <usb.h>
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#include <errno.h>
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#include <linux/compiler.h>
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#include <usb/ehci-fsl.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include "ehci.h"
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#define MX5_USBOTHER_REGS_OFFSET 0x800
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#define MXC_OTG_OFFSET 0
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#define MXC_H1_OFFSET 0x200
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#define MXC_H2_OFFSET 0x400
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#define MXC_H3_OFFSET 0x600
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#define MXC_USBCTRL_OFFSET 0
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#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
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#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
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#define MXC_USB_CTRL_1_OFFSET 0x10
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#define MXC_USBH2CTRL_OFFSET 0x14
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#define MXC_USBH3CTRL_OFFSET 0x18
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/* USB_CTRL */
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/* OTG wakeup intr enable */
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#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
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/* OTG power mask */
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#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
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/* OTG power pin polarity */
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#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
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/* Host1 ULPI interrupt enable */
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#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
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/* HOST1 wakeup intr enable */
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#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
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/* HOST1 power mask */
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#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
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/* HOST1 power pin polarity */
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#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
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/* USB_PHY_CTRL_FUNC */
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/* OTG Polarity of Overcurrent */
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#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
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/* OTG Disable Overcurrent Event */
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#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
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/* UH1 Polarity of Overcurrent */
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#define MXC_H1_OC_POL_BIT (1 << 6)
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/* UH1 Disable Overcurrent Event */
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#define MXC_H1_OC_DIS_BIT (1 << 5)
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/* OTG Power Pin Polarity */
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#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
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/* USBH2CTRL */
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#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
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#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
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#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
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#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
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#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
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#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
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/* USBH3CTRL */
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#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
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#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
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#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
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#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
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#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
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/* USB_CTRL_1 */
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#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
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int mxc_set_usbcontrol(int port, unsigned int flags)
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{
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unsigned int v;
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void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
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void __iomem *usbother_base;
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int ret = 0;
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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switch (port) {
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case 0: /* OTG port */
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if (flags & MXC_EHCI_INTERNAL_PHY) {
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v = __raw_readl(usbother_base +
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MXC_USB_PHY_CTR_FUNC_OFFSET);
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
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else
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v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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/* OC/USBPWR is used */
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v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
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else
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/* OC/USBPWR is not used */
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v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
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#ifdef CONFIG_MX51
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
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else
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v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
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#endif
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__raw_writel(v, usbother_base +
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MXC_USB_PHY_CTR_FUNC_OFFSET);
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v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
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#ifdef CONFIG_MX51
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_OTG_UCTRL_OPM_BIT;
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else
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v |= MXC_OTG_UCTRL_OPM_BIT;
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#endif
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#ifdef CONFIG_MX53
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
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else
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v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
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#endif
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__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
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}
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break;
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case 1: /* Host 1 ULPI */
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#ifdef CONFIG_MX51
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/* The clock for the USBH1 ULPI port will come externally
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from the PHY. */
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v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
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__raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
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MXC_USB_CTRL_1_OFFSET);
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#endif
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v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
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#ifdef CONFIG_MX51
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
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else
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v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
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#endif
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#ifdef CONFIG_MX53
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
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else
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v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
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#endif
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__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MXC_H1_OC_POL_BIT;
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else
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v &= ~MXC_H1_OC_POL_BIT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
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else
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v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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break;
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case 2: /* Host 2 ULPI */
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v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
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#ifdef CONFIG_MX51
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
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else
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v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
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#endif
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#ifdef CONFIG_MX53
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
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else
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v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
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else
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v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
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else
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v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
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#endif
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__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
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break;
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#ifdef CONFIG_MX53
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case 3: /* Host 3 ULPI */
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v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
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else
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v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
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else
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v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
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else
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v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
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__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
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break;
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#endif
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}
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return ret;
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}
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int __weak board_ehci_hcd_init(int port)
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{
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return 0;
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}
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void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
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{
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}
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int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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struct usb_ehci *ehci;
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#ifdef CONFIG_MX53
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struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR;
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u32 reg;
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reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
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/* derive USB PHY clock multiplexer from PLL3 */
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reg |= 1 << 26;
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__raw_writel(reg, &sc_regs->cscmr1);
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#endif
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set_usboh3_clk();
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enable_usboh3_clk(1);
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set_usb_phy_clk();
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enable_usb_phy1_clk(1);
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enable_usb_phy2_clk(1);
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mdelay(1);
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/* Do board specific initialization */
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board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
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ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
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(0x200 * CONFIG_MXC_USB_PORT));
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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setbits_le32(&ehci->usbmode, CM_HOST);
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__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
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mdelay(10);
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/* Do board specific post-initialization */
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board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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