upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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145 lines
3.4 KiB
145 lines
3.4 KiB
/*
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* (C) Copyright 2001-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This code should work for both the S3C2400 and the S3C2410
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* as they seem to have the same PLL and clock machinery inside.
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* The different address mapping is handled by the s3c24xx.h files below.
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*/
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#include <common.h>
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#include <asm/arch/s3c6400.h>
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#define APLL 0
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#define MPLL 1
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#define EPLL 2
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/* ------------------------------------------------------------------------- */
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/*
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* NOTE: This describes the proper use of this file.
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*
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* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
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*
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* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
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* the specified bus in HZ.
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*/
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/* ------------------------------------------------------------------------- */
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static ulong get_PLLCLK(int pllreg)
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{
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ulong r, m, p, s;
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switch (pllreg) {
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case APLL:
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r = APLL_CON_REG;
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break;
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case MPLL:
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r = MPLL_CON_REG;
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break;
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case EPLL:
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r = EPLL_CON0_REG;
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break;
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default:
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hang();
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}
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m = (r >> 16) & 0x3ff;
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p = (r >> 8) & 0x3f;
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s = r & 0x7;
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return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
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}
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/* return ARMCORE frequency */
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ulong get_ARMCLK(void)
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{
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ulong div;
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div = CLK_DIV0_REG;
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return get_PLLCLK(APLL) / ((div & 0x7) + 1);
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}
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/* return FCLK frequency */
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ulong get_FCLK(void)
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{
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return get_PLLCLK(APLL);
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}
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/* return HCLK frequency */
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ulong get_HCLK(void)
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{
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ulong fclk;
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uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
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uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
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/*
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* Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
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* s3c6400 and is always 0, and it is indeed running in ASYNC mode
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*/
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if (OTHERS_REG & 0x80)
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fclk = get_FCLK(); /* SYNC Mode */
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else
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fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
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return fclk / (hclk_div * hclkx2_div);
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}
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/* return PCLK frequency */
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ulong get_PCLK(void)
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{
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ulong fclk;
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uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
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uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
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if (OTHERS_REG & 0x80)
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fclk = get_FCLK(); /* SYNC Mode */
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else
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fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
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return fclk / (hclkx2_div * pre_div);
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}
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/* return UCLK frequency */
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ulong get_UCLK(void)
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{
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return get_PLLCLK(EPLL);
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}
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int print_cpuinfo(void)
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{
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printf("\nCPU: S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
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printf(" Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
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get_FCLK() / 1000000, get_HCLK() / 1000000,
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get_PCLK() / 1000000);
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if (OTHERS_REG & 0x80)
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printf("(SYNC Mode) \n");
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else
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printf("(ASYNC Mode) \n");
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return 0;
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}
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