upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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508 lines
12 KiB
508 lines
12 KiB
/*
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* Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
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* Jens Scharsig (esw@bus-elektronik.de)
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*
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* (C) Copyright 2003
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* Author : Hamid Ikdoumi (Atmel)
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_emac.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/at91_pio.h>
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#include <net.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <linux/mii.h>
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#undef MII_DEBUG
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#undef ET_DEBUG
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#if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
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#error AT91 EMAC supports max 1024 RX buffers. \
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Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
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#endif
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#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
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#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
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#endif
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/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
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#if (AT91C_MASTER_CLOCK > 80000000)
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_64
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#elif (AT91C_MASTER_CLOCK > 40000000)
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_32
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#elif (AT91C_MASTER_CLOCK > 20000000)
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_16
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#else
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_8
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#endif
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#ifdef ET_DEBUG
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#define DEBUG_AT91EMAC 1
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#else
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#define DEBUG_AT91EMAC 0
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#endif
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#ifdef MII_DEBUG
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#define DEBUG_AT91PHY 1
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#else
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#define DEBUG_AT91PHY 0
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#endif
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#ifndef CONFIG_DRIVER_AT91EMAC_QUIET
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#define VERBOSEP 1
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#else
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#define VERBOSEP 0
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#endif
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#define RBF_ADDR 0xfffffffc
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#define RBF_OWNER (1<<0)
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#define RBF_WRAP (1<<1)
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#define RBF_BROADCAST (1<<31)
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#define RBF_MULTICAST (1<<30)
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#define RBF_UNICAST (1<<29)
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#define RBF_EXTERNAL (1<<28)
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#define RBF_UNKNOWN (1<<27)
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#define RBF_SIZE 0x07ff
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#define RBF_LOCAL4 (1<<26)
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#define RBF_LOCAL3 (1<<25)
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#define RBF_LOCAL2 (1<<24)
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#define RBF_LOCAL1 (1<<23)
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#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
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#define RBF_FRAMELEN 0x600
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typedef struct {
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unsigned long addr, size;
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} rbf_t;
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typedef struct {
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rbf_t rbfdt[RBF_FRAMEMAX];
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unsigned long rbindex;
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} emac_device;
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void at91emac_EnableMDIO(at91_emac_t *at91mac)
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{
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/* Mac CTRL reg set for MDIO enable */
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writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
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}
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void at91emac_DisableMDIO(at91_emac_t *at91mac)
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{
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/* Mac CTRL reg set for MDIO disable */
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writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
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}
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int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
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unsigned char reg, unsigned short *value)
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{
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unsigned long netstat;
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at91emac_EnableMDIO(at91mac);
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writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
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AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
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AT91_EMAC_MAN_PHYA(addr),
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&at91mac->man);
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do {
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netstat = readl(&at91mac->sr);
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debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
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} while (!(netstat & AT91_EMAC_SR_IDLE));
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*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
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at91emac_DisableMDIO(at91mac);
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debug_cond(DEBUG_AT91PHY,
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"AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value);
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return 0;
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}
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int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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unsigned long netstat;
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debug_cond(DEBUG_AT91PHY,
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"AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value);
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at91emac_EnableMDIO(at91mac);
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writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
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AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
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AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
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&at91mac->man);
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do {
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netstat = readl(&at91mac->sr);
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debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
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} while (!(netstat & AT91_EMAC_SR_IDLE));
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at91emac_DisableMDIO(at91mac);
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return 0;
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}
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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at91_emac_t *get_emacbase_by_name(const char *devname)
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{
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struct eth_device *netdev;
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netdev = eth_get_dev_by_name(devname);
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return (at91_emac_t *) netdev->iobase;
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}
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int at91emac_mii_read(const char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value)
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{
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at91_emac_t *emac;
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emac = get_emacbase_by_name(devname);
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at91emac_read(emac , addr, reg, value);
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return 0;
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}
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int at91emac_mii_write(const char *devname, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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at91_emac_t *emac;
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emac = get_emacbase_by_name(devname);
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at91emac_write(emac, addr, reg, value);
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return 0;
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}
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#endif
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static int at91emac_phy_reset(struct eth_device *netdev)
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{
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int i;
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u16 status, adv;
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at91_emac_t *emac;
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emac = (at91_emac_t *) netdev->iobase;
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adv = ADVERTISE_CSMA | ADVERTISE_ALL;
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at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
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MII_ADVERTISE, adv);
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debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name);
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at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
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(BMCR_ANENABLE | BMCR_ANRESTART));
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for (i = 0; i < 30000; i++) {
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at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
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MII_BMSR, &status);
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if (status & BMSR_ANEGCOMPLETE)
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break;
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udelay(100);
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}
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if (status & BMSR_ANEGCOMPLETE) {
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debug_cond(VERBOSEP,
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"%s: Autonegotiation complete\n", netdev->name);
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} else {
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printf("%s: Autonegotiation timed out (status=0x%04x)\n",
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netdev->name, status);
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return -1;
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}
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return 0;
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}
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static int at91emac_phy_init(struct eth_device *netdev)
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{
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u16 phy_id, status, adv, lpa;
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int media, speed, duplex;
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int i;
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at91_emac_t *emac;
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emac = (at91_emac_t *) netdev->iobase;
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/* Check if the PHY is up to snuff... */
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at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
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MII_PHYSID1, &phy_id);
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if (phy_id == 0xffff) {
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printf("%s: No PHY present\n", netdev->name);
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return -1;
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}
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at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
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MII_BMSR, &status);
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if (!(status & BMSR_LSTATUS)) {
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/* Try to re-negotiate if we don't have link already. */
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if (at91emac_phy_reset(netdev))
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return -2;
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for (i = 0; i < 100000 / 100; i++) {
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at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
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MII_BMSR, &status);
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if (status & BMSR_LSTATUS)
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break;
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udelay(100);
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}
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}
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if (!(status & BMSR_LSTATUS)) {
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debug_cond(VERBOSEP, "%s: link down\n", netdev->name);
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return -3;
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} else {
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at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
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MII_ADVERTISE, &adv);
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at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
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MII_LPA, &lpa);
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media = mii_nway_result(lpa & adv);
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speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
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? 1 : 0);
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duplex = (media & ADVERTISE_FULL) ? 1 : 0;
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debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n",
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netdev->name,
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speed ? "100" : "10",
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duplex ? "full" : "half");
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}
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return 0;
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}
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int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
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{
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unsigned short stat1;
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at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
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if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
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return -1;
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if (stat1 & BMSR_100FULL) {
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/*set Emac for 100BaseTX and Full Duplex */
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writel(readl(&emac->cfg) |
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AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
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&emac->cfg);
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return 0;
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}
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if (stat1 & BMSR_10FULL) {
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/*set MII for 10BaseT and Full Duplex */
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writel((readl(&emac->cfg) &
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~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
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) | AT91_EMAC_CFG_FD,
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&emac->cfg);
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return 0;
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}
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if (stat1 & BMSR_100HALF) {
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/*set MII for 100BaseTX and Half Duplex */
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writel((readl(&emac->cfg) &
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~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
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) | AT91_EMAC_CFG_SPD,
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&emac->cfg);
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return 0;
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}
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if (stat1 & BMSR_10HALF) {
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/*set MII for 10BaseT and Half Duplex */
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writel((readl(&emac->cfg) &
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~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
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&emac->cfg);
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return 0;
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}
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return 0;
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}
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static int at91emac_init(struct eth_device *netdev, bd_t *bd)
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{
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int i;
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u32 value;
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emac_device *dev;
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at91_emac_t *emac;
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
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emac = (at91_emac_t *) netdev->iobase;
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dev = (emac_device *) netdev->priv;
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/* PIO Disable Register */
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value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC |
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ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 |
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ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS |
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ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 |
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ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK;
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writel(value, &pio->pioa.pdr);
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writel(value, &pio->pioa.asr);
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#ifdef CONFIG_RMII
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value = ATMEL_PMX_BA_ERXCK;
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#else
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value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL |
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ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 |
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ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER |
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ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2;
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#endif
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writel(value, &pio->piob.pdr);
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writel(value, &pio->piob.bsr);
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
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/* Init Ethernet buffers */
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for (i = 0; i < RBF_FRAMEMAX; i++) {
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dev->rbfdt[i].addr = (unsigned long) net_rx_packets[i];
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dev->rbfdt[i].size = 0;
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}
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dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
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dev->rbindex = 0;
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writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
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writel(readl(&emac->rsr) &
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~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
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&emac->rsr);
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value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC |
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HCLK_DIV;
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#ifdef CONFIG_RMII
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value |= AT91_EMAC_CFG_RMII;
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#endif
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writel(value, &emac->cfg);
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writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
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&emac->ctl);
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if (!at91emac_phy_init(netdev)) {
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at91emac_UpdateLinkSpeed(emac);
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return 0;
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}
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return -1;
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}
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static void at91emac_halt(struct eth_device *netdev)
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{
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at91_emac_t *emac;
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emac = (at91_emac_t *) netdev->iobase;
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writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
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&emac->ctl);
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debug_cond(DEBUG_AT91EMAC, "halt MAC\n");
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}
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static int at91emac_send(struct eth_device *netdev, void *packet, int length)
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{
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at91_emac_t *emac;
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emac = (at91_emac_t *) netdev->iobase;
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while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
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;
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writel((u32) packet, &emac->tar);
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writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
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while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
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;
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debug_cond(DEBUG_AT91EMAC, "Send %d\n", length);
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writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
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return 0;
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}
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static int at91emac_recv(struct eth_device *netdev)
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{
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emac_device *dev;
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at91_emac_t *emac;
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rbf_t *rbfp;
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int size;
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emac = (at91_emac_t *) netdev->iobase;
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dev = (emac_device *) netdev->priv;
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rbfp = &dev->rbfdt[dev->rbindex];
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while (rbfp->addr & RBF_OWNER) {
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size = rbfp->size & RBF_SIZE;
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net_process_received_packet(net_rx_packets[dev->rbindex], size);
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debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n",
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dev->rbindex, size, rbfp->addr);
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rbfp->addr &= ~RBF_OWNER;
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rbfp->size = 0;
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if (dev->rbindex < (RBF_FRAMEMAX-1))
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dev->rbindex++;
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else
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dev->rbindex = 0;
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rbfp = &(dev->rbfdt[dev->rbindex]);
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if (!(rbfp->addr & RBF_OWNER))
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writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
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&emac->rsr);
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}
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if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
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/* EMAC silicon bug 41.3.1 workaround 1 */
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writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
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writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
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dev->rbindex = 0;
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printf("%s: reset receiver (EMAC dead lock bug)\n",
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netdev->name);
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}
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return 0;
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}
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static int at91emac_write_hwaddr(struct eth_device *netdev)
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{
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at91_emac_t *emac;
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emac = (at91_emac_t *) netdev->iobase;
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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debug_cond(DEBUG_AT91EMAC,
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"init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
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netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],
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netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]);
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writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 |
|
|
netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24),
|
|
&emac->sa2l);
|
|
writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h);
|
|
debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n",
|
|
readl(&emac->sa2h), readl(&emac->sa2l));
|
|
return 0;
|
|
}
|
|
|
|
int at91emac_register(bd_t *bis, unsigned long iobase)
|
|
{
|
|
emac_device *emac;
|
|
emac_device *emacfix;
|
|
struct eth_device *dev;
|
|
|
|
if (iobase == 0)
|
|
iobase = ATMEL_BASE_EMAC;
|
|
emac = malloc(sizeof(*emac)+512);
|
|
if (emac == NULL)
|
|
return -1;
|
|
dev = malloc(sizeof(*dev));
|
|
if (dev == NULL) {
|
|
free(emac);
|
|
return -1;
|
|
}
|
|
/* alignment as per Errata (64 bytes) is insufficient! */
|
|
emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
|
|
memset(emacfix, 0, sizeof(emac_device));
|
|
|
|
memset(dev, 0, sizeof(*dev));
|
|
strcpy(dev->name, "emac");
|
|
dev->iobase = iobase;
|
|
dev->priv = emacfix;
|
|
dev->init = at91emac_init;
|
|
dev->halt = at91emac_halt;
|
|
dev->send = at91emac_send;
|
|
dev->recv = at91emac_recv;
|
|
dev->write_hwaddr = at91emac_write_hwaddr;
|
|
|
|
eth_register(dev);
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);
|
|
#endif
|
|
return 1;
|
|
}
|
|
|