upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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555 lines
16 KiB
555 lines
16 KiB
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "../board/freescale/common/ics307_clk.h"
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#ifdef CONFIG_36BIT
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#define CONFIG_PHYS_64BIT
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE /* BOOKE */
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#define CONFIG_E500 /* BOOKE e500 family */
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#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
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#define CONFIG_P1022
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#define CONFIG_P1022DS
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#define CONFIG_MP /* support multiple processors */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff80000
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
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#define CONFIG_PCI /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
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#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ENABLE_36BIT_PHYS
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#define CONFIG_ADDR_MAP
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE
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#define CONFIG_BTB
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#define CONFIG_SYS_MEMTEST_START 0x00000000
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#define CONFIG_SYS_MEMTEST_END 0x7fffffff
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
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#else
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
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#endif
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
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/* DDR Setup */
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#define CONFIG_DDR_SPD
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_FSL_DDR3
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#ifdef CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
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/* I2C addresses of SPD EEPROMs */
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#define CONFIG_SYS_SPD_BUS_NUM 1
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#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
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* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
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* 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
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*
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* Localbus cacheable (TBD)
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* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
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*
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* Localbus non-cacheable
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* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
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* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
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* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
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* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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*/
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_FLASH_BR_PRELIM \
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(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#define CONFIG_SYS_BR1_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
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#define CONFIG_SYS_FLASH_BANKS_LIST \
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{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_MAX_FLASH_SECT 1024
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_MISC_INIT_R
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#define CONFIG_HWCONFIG
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#define CONFIG_FSL_NGPIXIS
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#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
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#ifdef CONFIG_PHYS_64BIT
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#define PIXIS_BASE_PHYS 0xfffdf0000ull
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#else
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#define PIXIS_BASE_PHYS PIXIS_BASE
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#endif
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#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
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#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
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#define PIXIS_LBMAP_SWITCH 7
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#define PIXIS_LBMAP_MASK 0xF0
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#define PIXIS_LBMAP_ALTBANK 0x20
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#define PIXIS_ELBC_SPI_MASK 0xc0
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#define PIXIS_SPI 0x80
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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/* Video */
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#define CONFIG_FSL_DIU_FB
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#ifdef CONFIG_FSL_DIU_FB
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#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
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#define CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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/*
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* With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
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* disable empty flash sector detection, which is I/O-intensive.
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*/
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#undef CONFIG_SYS_FLASH_EMPTY_INFO
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#endif
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#ifndef CONFIG_FSL_DIU_FB
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#define CONFIG_ATI
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#endif
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#ifdef CONFIG_ATI
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#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
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#define CONFIG_VIDEO
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#define CONFIG_BIOSEMU
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_ATI_RADEON_FB
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#endif
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/*
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* Pass open firmware flat tree
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*/
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_OF_STDOUT_VIA_ALIAS
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/* new uImage format support */
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#define CONFIG_FIT
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#define CONFIG_FIT_VERBOSE
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/* I2C */
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#define CONFIG_FSL_I2C
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#define CONFIG_HARD_I2C
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_SPEED 400000
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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/*
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* I2C2 EEPROM
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*/
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_BUS_NUM 1
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_HARD_SPI
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#define CONFIG_FSL_ESPI
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#define CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE 0
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 1, Slot 2, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
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#else
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
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#endif
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
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#else
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
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#endif
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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/* controller 2, direct to uli, tgtid 2, Base address 9000 */
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
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#else
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
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#endif
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 3, Slot 1, tgtid 3, Base address b000 */
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
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#else
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#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
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#endif
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
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#else
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
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#endif
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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#ifdef CONFIG_PCI
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
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#endif
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/* SATA */
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#define CONFIG_LIBATA
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#define CONFIG_FSL_SATA
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#define CONFIG_FSL_SATA_V2
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_SATA1
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#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
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#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
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#define CONFIG_SATA2
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#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
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#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
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#ifdef CONFIG_FSL_SATA
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#define CONFIG_LBA48
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#define CONFIG_CMD_SATA
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_EXT2
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#endif
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#define CONFIG_MMC
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#ifdef CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
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#endif
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#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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#endif
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#define CONFIG_TSEC_ENET
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#ifdef CONFIG_TSEC_ENET
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#define CONFIG_TSECV2
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#define CONFIG_NET_MULTI
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define TSEC1_PHY_ADDR 1
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#define TSEC2_PHY_ADDR 2
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
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#endif
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_LOADS_ECHO
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#define CONFIG_SYS_LOADS_BAUD_CHANGE
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_ERRATA
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SETEXPR
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#define CONFIG_CMD_REGINFO
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_NET
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#endif
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/*
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* USB
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*/
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#define CONFIG_USB_EHCI
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#ifdef CONFIG_USB_EHCI
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#define CONFIG_CMD_USB
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_USB_STORAGE
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#define CONFIG_CMD_FAT
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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#define CONFIG_HOSTNAME p1022ds
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#define CONFIG_ROOTPATH /opt/nfsroot
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#define CONFIG_BOOTFILE uImage
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#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
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#define CONFIG_LOADADDR 1000000
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#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
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#define CONFIG_BOOTARGS
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"perf_mode=stable\0" \
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"memctl_intlv_ctl=2\0" \
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"netdev=eth0\0" \
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"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
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"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=uramdisk\0" \
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"fdtaddr=c00000\0" \
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"fdtfile=p1022ds.dtb\0" \
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"bdev=sda3\0" \
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"diuregs=md e002c000 1d\0" \
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"dium=mw e002c01c\0" \
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"diuerr=md e002c014 1\0" \
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"hwconfig=esdhc;audclk:12\0"
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#define CONFIG_HDBOOT \
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"setenv bootargs root=/dev/$bdev rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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|
"setenv bootargs root=/dev/ram rw " \
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|
"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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|
"tftp $loadaddr $bootfile;" \
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|
"tftp $fdtaddr $fdtfile;" \
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|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
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#endif
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