upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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299 lines
6.0 KiB
299 lines
6.0 KiB
/*
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* (C) Copyright 2004
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* DAVE Srl
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/hardware.h>
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/*
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* Initialization, must be called once on start up, may be called
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* repeatedly to change the speed and slave addresses.
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*/
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void i2c_init(int speed, int slaveaddr)
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{
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/*
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setting up I2C support
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*/
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unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF;
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save_F = PCONF;
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save_PF = PUPF;
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rPCONF = ((save_F & ~(0xF))| 0xa);
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rPUPF = (save_PF | 0x3);
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PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/
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PUPF = rPUPF; /* Disable pull-up */
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/* Configuring pin for WC pin of EEprom */
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rPCONA = PCONA;
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rPCONA &= ~(1<<9);
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PCONA = rPCONA;
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rPDATA = PDATA;
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rPDATA &= ~(1<<9);
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PDATA = rPDATA;
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/*
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Enable ACK, IICCLK=MCLK/16, enable interrupt
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75MHz/16/(12+1) = 390625 Hz
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*/
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rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC);
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IICCON = rIICCON;
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IICADD = slaveaddr;
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}
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/*
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* Probe the given I2C chip address. Returns 0 if a chip responded,
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* not 0 on failure.
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*/
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int i2c_probe(uchar chip)
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{
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/*
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not implemented
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*/
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printf("i2c_probe chip %d\n", (int) chip);
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return -1;
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}
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/*
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* Read/Write interface:
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* chip: I2C chip address, range 0..127
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* addr: Memory (register) address within the chip
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* alen: Number of bytes to use for addr (typically 1, 2 for larger
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* memories, 0 for register type devices with only one
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* register)
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* buffer: Where to read/write the data
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* len: How many bytes to read/write
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*
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* Returns: 0 on success, not 0 on failure
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*/
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#define S3C44B0X_rIIC_INTPEND (1<<4)
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#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0)
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#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5)
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#define S3C44B0_IIC_TIMEOUT 100
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int k, j, temp;
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u32 rIICSTAT;
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/*
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send the device offset
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*/
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rIICSTAT = 0xD0;
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IICSTAT = rIICSTAT;
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IICDS = chip; /* this is a write operation... */
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rIICSTAT |= (1<<5);
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IICSTAT = rIICSTAT;
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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/* wait and check ACK */
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temp = IICSTAT;
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if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
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return -1;
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IICDS = addr;
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IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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/* wait and check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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temp = IICSTAT;
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if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
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return -1;
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/*
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now we can start with the read operation...
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*/
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IICDS = chip | 0x01; /* this is a read operation... */
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rIICSTAT = 0x90; /*master recv*/
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rIICSTAT |= (1<<5);
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IICSTAT = rIICSTAT;
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IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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/* wait and check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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temp = IICSTAT;
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if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
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return -1;
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for (j=0; j<len-1; j++) {
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/*clear pending bit to resume */
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temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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IICCON = temp;
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/* wait and check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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buffer[j] = IICDS; /*save readed data*/
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} /*end for(j)*/
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/*
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reading the last data
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unset ACK generation
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*/
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temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7));
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IICCON = temp;
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/* wait but NOT check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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buffer[j] = IICDS; /*save readed data*/
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rIICSTAT = 0x90; /*master recv*/
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/* Write operation Terminate sending STOP */
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IICSTAT = rIICSTAT;
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/*Clear Int Pending Bit to RESUME*/
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temp = IICCON;
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IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
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IICCON = IICCON | (1<<7); /*restore ACK generation*/
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return 0;
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}
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int j, k;
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u32 rIICSTAT, temp;
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/*
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send the device offset
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*/
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rIICSTAT = 0xD0;
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IICSTAT = rIICSTAT;
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IICDS = chip; /* this is a write operation... */
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rIICSTAT |= (1<<5);
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IICSTAT = rIICSTAT;
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IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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/* wait and check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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temp = IICSTAT;
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if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
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return -1;
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IICDS = addr;
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IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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/* wait and check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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temp = IICSTAT;
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if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
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return -1;
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/*
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now we can start with the read write operation
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*/
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for (j=0; j<len; j++) {
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IICDS = buffer[j]; /*prerare data to write*/
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/*clear pending bit to resume*/
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temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
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IICCON = temp;
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/* wait but NOT check ACK */
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for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
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temp = IICCON;
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if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
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break;
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udelay(2000);
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}
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if (k==S3C44B0_IIC_TIMEOUT)
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return -1;
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} /* end for(j) */
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/* sending stop to terminate */
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rIICSTAT = 0xD0; /*master send*/
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IICSTAT = rIICSTAT;
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/*Clear Int Pending Bit to RESUME*/
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temp = IICCON;
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IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
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return 0;
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}
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