upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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298 lines
7.2 KiB
298 lines
7.2 KiB
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002
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* Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <ide.h>
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#include <netdev.h>
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#include "piix_pci.h"
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#include "eXalion.h"
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int checkboard (void)
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{
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ulong busfreq = get_bus_freq (0);
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char buf[32];
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printf ("Board: eXalion MPC824x - CHRP (MAP B)\n");
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printf ("Built: %s at %s\n", __DATE__, __TIME__);
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printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq));
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return 0;
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}
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int checkflash (void)
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{
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printf ("checkflash\n");
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flash_init ();
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return (0);
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}
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phys_size_t initdram (int board_type)
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{
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int i, cnt;
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volatile uchar *base = CONFIG_SYS_SDRAM_BASE;
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volatile ulong *addr;
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ulong save[32];
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ulong val, ret = 0;
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for (i = 0, cnt = (CONFIG_SYS_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
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cnt >>= 1) {
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addr = (volatile ulong *) base + cnt;
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save[i++] = *addr;
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*addr = ~cnt;
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}
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addr = (volatile ulong *) base;
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save[i] = *addr;
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*addr = 0;
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if (*addr != 0) {
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*addr = save[i];
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goto Done;
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}
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for (cnt = 1; cnt <= CONFIG_SYS_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
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addr = (volatile ulong *) base + cnt;
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val = *addr;
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*addr = save[--i];
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if (val != ~cnt) {
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ulong new_bank0_end = cnt * sizeof (long) - 1;
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ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
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ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
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mear1 = (mear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >>
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MICR_ADDR_SHIFT);
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emear1 = (emear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >>
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MICR_EADDR_SHIFT);
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mpc824x_mpc107_setreg (MEAR1, mear1);
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mpc824x_mpc107_setreg (EMEAR1, emear1);
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ret = cnt * sizeof (long);
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goto Done;
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}
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}
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ret = CONFIG_SYS_MAX_RAM_SIZE;
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Done:
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return ret;
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}
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int misc_init_r (void)
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{
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pci_dev_t bdf;
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u32 val32;
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u8 val8;
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puts ("ISA: ");
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bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0);
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if (bdf == -1) {
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puts ("Unable to find PIIX4 ISA bridge !\n");
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hang ();
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}
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/* set device for normal ISA instead EIO */
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pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32);
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val32 |= 0x00000001;
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pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32);
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printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf),
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PCI_DEV (bdf), PCI_FUNC (bdf));
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puts ("ISA: ");
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bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0);
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if (bdf == -1) {
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puts ("Unable to find PIIX4 IDE controller !\n");
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hang ();
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}
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/* Init BMIBA register */
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/* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */
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/* val32 |= 0x1000; */
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/* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */
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/* Enable BUS master and IO access */
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val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO;
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pci_write_config_dword (bdf, PCI_COMMAND, val32);
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/* Set latency */
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pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8);
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val8 = 0x40;
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pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8);
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/* Enable Primary ATA/IDE */
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pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32);
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/* val32 = 0xa307a307; */
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val32 = 0x00008000;
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pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32);
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printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf),
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PCI_DEV (bdf), PCI_FUNC (bdf));
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/* Try to get FAT working... */
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/* fat_register_read(ide_read); */
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return (0);
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}
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/*
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* Show/Init PCI devices on the specified bus number.
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*/
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void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned char line;
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switch (PCI_DEV (dev)) {
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case 16:
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line = PCI_INT_A;
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break;
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case 17:
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line = PCI_INT_B;
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break;
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case 18:
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line = PCI_INT_C;
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break;
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case 19:
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line = PCI_INT_D;
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break;
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#if defined (CONFIG_MPC8245)
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case 20:
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line = PCI_INT_A;
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break;
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case 21:
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line = PCI_INT_B;
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break;
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case 22:
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line = PCI_INT_NA;
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break;
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#endif
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default:
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line = PCI_INT_A;
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break;
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}
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pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line);
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}
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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#if defined (CONFIG_MPC8240)
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static struct pci_config_table pci_eXalion_config_table[] = {
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{
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/* Intel 82559ER ethernet controller */
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER}},
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{
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/* Intel 82371AB PIIX4 PCI to ISA bridge */
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
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pci_cfgfunc_config_device, {0,
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0,
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PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
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{
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/* Intel 82371AB PIIX4 IDE controller */
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01,
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pci_cfgfunc_config_device, {0,
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0,
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PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
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{}
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};
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#elif defined (CONFIG_MPC8245)
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static struct pci_config_table pci_eXalion_config_table[] = {
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{
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/* Intel 82559ER ethernet controller */
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00,
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER}},
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{
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/* Intel 82559ER ethernet controller */
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
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pci_cfgfunc_config_device, {PCI_ENET1_IOADDR,
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PCI_ENET1_MEMADDR,
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER}},
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{
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/* Broadcom BCM5690 Gigabit switch */
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
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pci_cfgfunc_config_device, {PCI_ENET2_IOADDR,
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PCI_ENET2_MEMADDR,
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER}},
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{
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/* Broadcom BCM5690 Gigabit switch */
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00,
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pci_cfgfunc_config_device, {PCI_ENET3_IOADDR,
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PCI_ENET3_MEMADDR,
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER}},
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{
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/* Intel 82371AB PIIX4 PCI to ISA bridge */
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00,
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pci_cfgfunc_config_device, {0,
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0,
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PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
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{
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/* Intel 82371AB PIIX4 IDE controller */
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01,
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pci_cfgfunc_config_device, {0,
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0,
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PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
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{}
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};
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#else
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#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
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#endif
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#endif /* #ifndef CONFIG_PCI_PNP */
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struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table:pci_eXalion_config_table,
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fixup_irq:pci_eXalion_fixup_irq,
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#endif
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};
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void pci_init_board (void)
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{
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pci_mpc824x_init (&hose);
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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