upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
167 lines
5.2 KiB
167 lines
5.2 KiB
/*
|
|
* Projectiondesign AS
|
|
* Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
|
|
*
|
|
* Copyright (C) 2011 Freescale Semiconductor, Inc.
|
|
* Jason Liu <r64343@freescale.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*
|
|
* Refer doc/README.imximage for more details about how-to configure
|
|
* and create imximage boot image
|
|
*
|
|
* The syntax is taken as close as possible with the kwbimage
|
|
*/
|
|
|
|
/* image version */
|
|
|
|
IMAGE_VERSION 2
|
|
|
|
/*
|
|
* Boot Device : one of
|
|
* sd, nand
|
|
*/
|
|
BOOT_FROM nand
|
|
|
|
/*
|
|
* Device Configuration Data (DCD)
|
|
*
|
|
* Each entry must have the format:
|
|
* Addr-type Address Value
|
|
*
|
|
* where:
|
|
* Addr-type register length (1,2 or 4 bytes)
|
|
* Address absolute address of the register
|
|
* value value to be stored in the register
|
|
*/
|
|
|
|
#define __ASSEMBLY__
|
|
#include <config.h>
|
|
#include "asm/arch/mx6-ddr.h"
|
|
#include "asm/arch/iomux.h"
|
|
#include "asm/arch/crm_regs.h"
|
|
|
|
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
|
|
|
|
DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
|
|
|
|
DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
|
|
|
|
DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
|
|
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
|
|
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
|
|
|
|
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
|
|
|
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
|
|
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
|
|
|
|
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
|
|
|
/* (differential input) */
|
|
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
|
/* disable ddr pullups */
|
|
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
|
/* (differential input) */
|
|
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
|
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
|
|
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
|
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
|
|
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
|
|
|
/* Read data DQ Byte0-3 delay */
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
|
|
|
|
/*
|
|
* MDMISC mirroring interleaved (row/bank/col)
|
|
*/
|
|
DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
|
|
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
|
DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
|
|
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
|
|
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
|
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
|
DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
|
|
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
|
|
DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
|
|
DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
|
|
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
|
|
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
|
|
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
|
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
|
|
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
|
|
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
|
|
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
|
|
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
|
|
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
|
|
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
|
|
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
|
|
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
|
|
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
|
|
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
|
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
|
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
|
|
|
/* set the default clock gate to save power */
|
|
DATA 4, CCM_CCGR0, 0x00C03F3F
|
|
DATA 4, CCM_CCGR1, 0x0030FC03
|
|
DATA 4, CCM_CCGR2, 0x0FFFC000
|
|
DATA 4, CCM_CCGR3, 0x3FF00000
|
|
DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
|
|
DATA 4, CCM_CCGR5, 0x0F0000C3
|
|
DATA 4, CCM_CCGR6, 0x000003FF
|
|
|
|
/* enable AXI cache for VDOA/VPU/IPU */
|
|
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
|
|
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
|
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
|
|
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
|
|
|