upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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132 lines
2.8 KiB
132 lines
2.8 KiB
/*
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* Copyright (C) 2016 samtec automotive software & electronics gmbh
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi/sd/nand/onenand, qspi/nor
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* Enable all clocks */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020c4084 0xffffffff
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/* IOMUX - DDR IO Type */
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DATA 4 0x020e0618 0x000c0000
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DATA 4 0x020e05fc 0x00000000
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/* Clock */
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DATA 4 0x020e032c 0x00000030
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/* Address */
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DATA 4 0x020e0300 0x00000028
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DATA 4 0x020e02fc 0x00000028
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DATA 4 0x020e05f4 0x00000028
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/* Control */
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DATA 4 0x020e0340 0x00000028
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DATA 4 0x020e0320 0x00000000
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DATA 4 0x020e0310 0x00000028
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DATA 4 0x020e0314 0x00000028
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DATA 4 0x020e0614 0x00000028
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/* Data Strobe */
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DATA 4 0x020e05f8 0x00020000
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DATA 4 0x020e0330 0x00000028
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DATA 4 0x020e0334 0x00000028
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DATA 4 0x020e0338 0x00000028
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DATA 4 0x020e033c 0x00000028
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/* Data */
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DATA 4 0x020e0608 0x00020000
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DATA 4 0x020e060c 0x00000028
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DATA 4 0x020e0610 0x00000028
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DATA 4 0x020e061c 0x00000028
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DATA 4 0x020e0620 0x00000028
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DATA 4 0x020e02ec 0x00000028
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DATA 4 0x020e02f0 0x00000028
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DATA 4 0x020e02f4 0x00000028
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DATA 4 0x020e02f8 0x00000028
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/* Calibrations - ZQ */
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DATA 4 0x021b0800 0xa1390003
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/* Write leveling */
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DATA 4 0x021b080c 0x00290025
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DATA 4 0x021b0810 0x00210022
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/* DQS Read Gate */
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DATA 4 0x021b083c 0x4142013a
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DATA 4 0x021b0840 0x012e0123
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/* Read/Write Delay */
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DATA 4 0x021b0848 0x43474949
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DATA 4 0x021b0850 0x38383c38
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/* Read data bit delay */
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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/* Complete calibration by forced measurement */
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DATA 4 0x021b08b8 0x00000800
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/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
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DATA 4 0x021b0004 0x0002002d
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DATA 4 0x021b0008 0x00333040
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DATA 4 0x021b000c 0x676b52f2
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DATA 4 0x021b0010 0x926e8b63
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DATA 4 0x021b0014 0x01ff00db
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DATA 4 0x021b0018 0x00011740
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b002c 0x000026d2
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DATA 4 0x021b0030 0x006b1023
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DATA 4 0x021b0040 0x0000005f
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DATA 4 0x021b0000 0x84190000
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/* Initialize MT41K256M16HA-125 - MR2 */
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DATA 4 0x021b001c 0x02008032
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/* MR3 */
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DATA 4 0x021b001c 0x00008033
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/* MR1 */
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DATA 4 0x021b001c 0x00048031
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/* MR0 */
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DATA 4 0x021b001c 0x15108030
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/* DDR device ZQ calibration */
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DATA 4 0x021b001c 0x04008040
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/* Final DDR setup, before operation start */
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DATA 4 0x021b0020 0x00007800
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DATA 4 0x021b0818 0x00022227
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DATA 4 0x021b001c 0x00000000
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