upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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298 lines
11 KiB
298 lines
11 KiB
/*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* yellowstone.h - configuration for YELLOWSTONE board
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */
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#define CONFIG_440GR 1 /* Specific PPC440GR support */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#undef CFG_DRAM_TEST /* disable - takes long time! */
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#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xf0000000 /* start of FLASH */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
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#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
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#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
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#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
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/*Don't change either of these*/
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#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
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#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
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/*Don't change either of these*/
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#define CFG_USB_DEVICE 0x50000000
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#define CFG_NVRAM_BASE_ADDR 0x80000000
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#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in SDRAM)
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*----------------------------------------------------------------------*/
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#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
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#define CFG_INIT_RAM_END 0x2000
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
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#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
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#define CFG_SDRAM_BANKS (2)
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_SERIAL_MULTI 1
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/*define this if you want console on UART1*/
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#undef CONFIG_UART1_CONSOLE
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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* NVRAM/RTC
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*
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* NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
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* The DS1558 code assumes this condition
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*
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*----------------------------------------------------------------------*/
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#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
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#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
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#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
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#define CFG_ENV_IS_IN_EEPROM 1
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/* Define to allow the user to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CFG_I2C_MULTI_EEPROMS
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#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
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#define CFG_ENV_OFFSET 0x0
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#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
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#define CONFIG_BOOTDELAY 3 /* disable autoboot */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_NET_MULTI 1 /* required for netconsole */
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#define CONFIG_PHY1_ADDR 3
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 10.0.4.251
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#define CONFIG_ETHADDR 00:10:EC:00:12:34
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#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_SERVERIP 10.0.4.115
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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#ifdef CONFIG_440EP
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/* USB */
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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/*Comment this out to enable USB 1.1 device*/
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#define USB_2_0_DEVICE
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#endif /*CONFIG_440EP*/
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#ifdef DEBUG
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#define CONFIG_PANIC_HANG
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#else
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#define CONFIG_HW_WATCHDOG /* watchdog */
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#endif
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#ifdef CONFIG_440EP
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/* Need to define POST */
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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CFG_CMD_ECHO | \
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CFG_CMD_EEPROM | \
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CFG_CMD_ELF | \
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/* CFG_CMD_EXT2 |*/ \
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/* CFG_CMD_FAT |*/ \
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CFG_CMD_I2C | \
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/* CFG_CMD_IDE |*/ \
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CFG_CMD_IRQ | \
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/* CFG_CMD_KGDB |*/ \
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CFG_CMD_MII | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_FLASH | \
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/* CFG_CMD_SPI |*/ \
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CFG_CMD_USB | \
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0 ) & ~CFG_CMD_IMLS)
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#else
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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CFG_CMD_ECHO | \
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CFG_CMD_EEPROM | \
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CFG_CMD_ELF | \
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/* CFG_CMD_EXT2 |*/ \
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/* CFG_CMD_FAT |*/ \
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CFG_CMD_I2C | \
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/* CFG_CMD_IDE |*/ \
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CFG_CMD_IRQ | \
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/* CFG_CMD_KGDB |*/ \
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CFG_CMD_MII | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_FLASH | \
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/* CFG_CMD_SPI |*/ \
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0 ) & ~CFG_CMD_IMLS)
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#endif
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_LYNXKDI 1 /* support kdi files */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
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/* Board-specific PCI */
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#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
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#define CFG_PCI_TARGET_INIT
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#define CFG_PCI_MASTER_INIT
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#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
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#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#endif /* __CONFIG_H */
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