upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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75 lines
1.7 KiB
75 lines
1.7 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010
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* Armando Visconti, ST Micoelectronics, <armando.visconti@st.com>.
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*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <usb.h>
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#include "ehci.h"
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_misc.h>
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static void spear6xx_usbh_stop(void)
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{
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struct misc_regs *const misc_p =
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(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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u32 periph1_rst = readl(misc_p->periph1_rst);
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periph1_rst |= PERIPH_USBH1 | PERIPH_USBH2;
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writel(periph1_rst, misc_p->periph1_rst);
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udelay(1000);
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periph1_rst &= ~(PERIPH_USBH1 | PERIPH_USBH2);
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writel(periph1_rst, misc_p->periph1_rst);
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}
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/*
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* Create the appropriate control structures to manage
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* a new EHCI host controller.
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*/
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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u32 ehci = 0;
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switch (index) {
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case 0:
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ehci = CONFIG_SYS_UHC0_EHCI_BASE;
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break;
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case 1:
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ehci = CONFIG_SYS_UHC1_EHCI_BASE;
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break;
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default:
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printf("ERROR: wrong controller index!\n");
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break;
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};
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*hccr = (struct ehci_hccr *)(ehci + 0x100);
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*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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debug("SPEAr-ehci: init hccr %x and hcor %x hc_length %d\n",
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(uint32_t)*hccr, (uint32_t)*hcor,
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(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(int index)
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{
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#if defined(CONFIG_SPEAR600)
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spear6xx_usbh_stop();
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#endif
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return 0;
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}
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