upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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79 lines
1.8 KiB
79 lines
1.8 KiB
/*
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* COM1 NS16550 support
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* originally from linux source (arch/ppc/boot/ns16550.c)
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* modified to use CONFIG_SYS_ISA_MEM and new defines
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*/
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#include <config.h>
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#ifdef CONFIG_SYS_NS16550
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#include <ns16550.h>
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#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */
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#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */
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#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */
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void NS16550_init (NS16550_t com_port, int baud_divisor)
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{
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com_port->ier = 0x00;
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#ifdef CONFIG_OMAP
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com_port->mdr1 = 0x7; /* mode select reset TL16C750*/
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#endif
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com_port->lcr = LCR_BKSE | LCRVAL;
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com_port->dll = 0;
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com_port->dlm = 0;
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com_port->lcr = LCRVAL;
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com_port->mcr = MCRVAL;
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com_port->fcr = FCRVAL;
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com_port->lcr = LCR_BKSE | LCRVAL;
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com_port->dll = baud_divisor & 0xff;
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com_port->dlm = (baud_divisor >> 8) & 0xff;
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com_port->lcr = LCRVAL;
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#if defined(CONFIG_OMAP)
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#if defined(CONFIG_APTIX)
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com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */
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#else
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com_port->mdr1 = 0; /* /16 is proper to hit 115200 with 48MHz */
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#endif
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#endif
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}
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void NS16550_reinit (NS16550_t com_port, int baud_divisor)
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{
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com_port->ier = 0x00;
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com_port->lcr = LCR_BKSE | LCRVAL;
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com_port->dll = 0;
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com_port->dlm = 0;
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com_port->lcr = LCRVAL;
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com_port->mcr = MCRVAL;
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com_port->fcr = FCRVAL;
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com_port->lcr = LCR_BKSE;
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com_port->dll = baud_divisor & 0xff;
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com_port->dlm = (baud_divisor >> 8) & 0xff;
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com_port->lcr = LCRVAL;
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}
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void NS16550_putc (NS16550_t com_port, char c)
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{
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while ((com_port->lsr & LSR_THRE) == 0);
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com_port->thr = c;
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}
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char NS16550_getc (NS16550_t com_port)
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{
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while ((com_port->lsr & LSR_DR) == 0) {
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#ifdef CONFIG_USB_TTY
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extern void usbtty_poll(void);
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usbtty_poll();
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#endif
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}
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return (com_port->rbr);
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}
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int NS16550_tstc (NS16550_t com_port)
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{
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return ((com_port->lsr & LSR_DR) != 0);
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}
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#endif
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