upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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635 lines
15 KiB
635 lines
15 KiB
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* m8xx.c
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*
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* CPU specific code
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*
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* written or collected and sometimes rewritten by
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* Magnus Damm <damm@bitsmart.com>
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*
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* minor modifications by
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* Wolfgang Denk <wd@denx.de>
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <mpc8xx.h>
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#include <commproc.h>
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#include <netdev.h>
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#include <asm/cache.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <fdt_support.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static char *cpu_warning = "\n " \
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"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
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#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
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!defined(CONFIG_MPC862))
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static int check_CPU (long clock, uint pvr, uint immr)
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{
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char *id_str =
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# if defined(CONFIG_MPC855)
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"PC855";
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# elif defined(CONFIG_MPC860P)
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"PC860P";
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# else
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NULL;
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# endif
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volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
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uint k, m;
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char buf[32];
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char pre = 'X';
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char *mid = "xx";
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char *suf;
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/* the highest 16 bits should be 0x0050 for a 860 */
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if ((pvr >> 16) != 0x0050)
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return -1;
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k = (immr << 16) |
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immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
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m = 0;
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suf = "";
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/*
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* Some boards use sockets so different CPUs can be used.
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* We have to check chip version in run time.
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*/
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switch (k) {
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case 0x00020001: pre = 'P'; break;
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case 0x00030001: break;
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case 0x00120003: suf = "A"; break;
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case 0x00130003: suf = "A3"; break;
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case 0x00200004: suf = "B"; break;
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case 0x00300004: suf = "C"; break;
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case 0x00310004: suf = "C1"; m = 1; break;
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case 0x00200064: mid = "SR"; suf = "B"; break;
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case 0x00300065: mid = "SR"; suf = "C"; break;
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case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
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case 0x05010000: suf = "D3"; m = 1; break;
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case 0x05020000: suf = "D4"; m = 1; break;
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/* this value is not documented anywhere */
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case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
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/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
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case 0x08010004: /* Rev. A.0 */
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suf = "A";
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/* fall through */
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case 0x08000003: /* Rev. 0.3 */
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pre = 'M'; m = 1;
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if (id_str == NULL)
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id_str =
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# if defined(CONFIG_MPC859T)
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"PC859T";
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# else
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"PC866x"; /* Unknown chip from MPC866 family */
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# endif
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break;
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case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
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if (id_str == NULL)
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id_str = "PC885"; /* 870/875/880/885 */
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break;
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default: suf = NULL; break;
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}
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if (id_str == NULL)
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id_str = "PC86x"; /* Unknown 86x chip */
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if (suf)
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printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
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else
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printf ("unknown M%s (0x%08x)", id_str, k);
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#if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
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printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
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strmhz (buf, clock),
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CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
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((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
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CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
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((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
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);
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#else
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printf (" at %s MHz: ", strmhz (buf, clock));
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#endif
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print_size(checkicache(), " I-Cache ");
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print_size(checkdcache(), " D-Cache");
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/* do we have a FEC (860T/P or 852/859/866/885)? */
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immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
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if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
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printf (" FEC present");
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}
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if (!m) {
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puts (cpu_warning);
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}
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putc ('\n');
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#ifdef DEBUG
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if(clock != measure_gclk()) {
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printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
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}
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#endif
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return 0;
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}
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#elif defined(CONFIG_MPC862)
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static int check_CPU (long clock, uint pvr, uint immr)
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{
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volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
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uint k, m;
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char buf[32];
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char pre = 'X';
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__maybe_unused char *mid = "xx";
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char *suf;
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/* the highest 16 bits should be 0x0050 for a 8xx */
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if ((pvr >> 16) != 0x0050)
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return -1;
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k = (immr << 16) |
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immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
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m = 0;
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switch (k) {
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/* this value is not documented anywhere */
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case 0x06000000: mid = "P"; suf = "0"; break;
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case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
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case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
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default: suf = NULL; break;
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}
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#ifndef CONFIG_MPC857
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if (suf)
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printf ("%cPC862%sZPnn%s", pre, mid, suf);
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else
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printf ("unknown MPC862 (0x%08x)", k);
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#else
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if (suf)
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printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
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else
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printf ("unknown MPC857 (0x%08x)", k);
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#endif
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printf(" at %s MHz: ", strmhz(buf, clock));
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print_size(checkicache(), " I-Cache ");
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print_size(checkdcache(), " D-Cache");
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/* lets check and see if we're running on a 862T (or P?) */
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immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
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if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
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printf (" FEC present");
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}
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if (!m) {
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puts (cpu_warning);
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}
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putc ('\n');
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return 0;
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}
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#elif defined(CONFIG_MPC823)
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static int check_CPU (long clock, uint pvr, uint immr)
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{
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volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
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uint k, m;
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char buf[32];
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char *suf;
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/* the highest 16 bits should be 0x0050 for a 8xx */
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if ((pvr >> 16) != 0x0050)
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return -1;
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k = (immr << 16) |
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in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
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m = 0;
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switch (k) {
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/* MPC823 */
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case 0x20000000: suf = "0"; break;
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case 0x20010000: suf = "0.1"; break;
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case 0x20020000: suf = "Z2/3"; break;
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case 0x20020001: suf = "Z3"; break;
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case 0x21000000: suf = "A"; break;
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case 0x21010000: suf = "B"; m = 1; break;
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case 0x21010001: suf = "B2"; m = 1; break;
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/* MPC823E */
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case 0x24010000: suf = NULL;
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puts ("PPC823EZTnnB2");
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m = 1;
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break;
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default:
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suf = NULL;
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printf ("unknown MPC823 (0x%08x)", k);
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break;
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}
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if (suf)
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printf ("PPC823ZTnn%s", suf);
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printf(" at %s MHz: ", strmhz(buf, clock));
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print_size(checkicache(), " I-Cache ");
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print_size(checkdcache(), " D-Cache");
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/* lets check and see if we're running on a 860T (or P?) */
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immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
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if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
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puts (" FEC present");
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}
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if (!m) {
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puts (cpu_warning);
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}
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putc ('\n');
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return 0;
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}
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#elif defined(CONFIG_MPC850)
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static int check_CPU (long clock, uint pvr, uint immr)
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{
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volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
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uint k, m;
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char buf[32];
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/* the highest 16 bits should be 0x0050 for a 8xx */
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if ((pvr >> 16) != 0x0050)
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return -1;
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k = (immr << 16) |
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immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
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m = 0;
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switch (k) {
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case 0x20020001:
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printf ("XPC850xxZT");
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break;
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case 0x21000065:
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printf ("XPC850xxZTA");
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break;
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case 0x21010067:
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printf ("XPC850xxZTB");
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m = 1;
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break;
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case 0x21020068:
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printf ("XPC850xxZTC");
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m = 1;
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break;
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default:
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printf ("unknown MPC850 (0x%08x)", k);
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}
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printf(" at %s MHz: ", strmhz(buf, clock));
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print_size(checkicache(), " I-Cache ");
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print_size(checkdcache(), " D-Cache");
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/* lets check and see if we're running on a 850T (or P?) */
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immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
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if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
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printf (" FEC present");
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}
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if (!m) {
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puts (cpu_warning);
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}
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putc ('\n');
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return 0;
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}
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#else
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#error CPU undefined
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#endif
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/* ------------------------------------------------------------------------- */
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int checkcpu (void)
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{
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ulong clock = gd->cpu_clk;
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uint immr = get_immr (0); /* Return full IMMR contents */
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uint pvr = get_pvr ();
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puts ("CPU: ");
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/* 850 has PARTNUM 20 */
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/* 801 has PARTNUM 10 */
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return check_CPU (clock, pvr, immr);
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}
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/* ------------------------------------------------------------------------- */
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/* L1 i-cache */
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/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
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/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
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int checkicache (void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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u32 cacheon = rd_ic_cst () & IDC_ENABLED;
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#ifdef CONFIG_IP86x
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u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
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#else
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u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
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#endif
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u32 m;
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u32 lines = -1;
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wr_ic_cst (IDC_UNALL);
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wr_ic_cst (IDC_INVALL);
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wr_ic_cst (IDC_DISABLE);
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__asm__ volatile ("isync");
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while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
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wr_ic_adr (k);
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wr_ic_cst (IDC_LDLCK);
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__asm__ volatile ("isync");
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lines++;
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k += 0x10; /* the number of bytes in a cacheline */
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}
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wr_ic_cst (IDC_UNALL);
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wr_ic_cst (IDC_INVALL);
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if (cacheon)
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wr_ic_cst (IDC_ENABLE);
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else
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wr_ic_cst (IDC_DISABLE);
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__asm__ volatile ("isync");
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return lines << 4;
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};
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/* ------------------------------------------------------------------------- */
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/* L1 d-cache */
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/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
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/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
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/* call with cache disabled */
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int checkdcache (void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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u32 cacheon = rd_dc_cst () & IDC_ENABLED;
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#ifdef CONFIG_IP86x
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u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
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#else
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u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
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#endif
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u32 m;
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u32 lines = -1;
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wr_dc_cst (IDC_UNALL);
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wr_dc_cst (IDC_INVALL);
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wr_dc_cst (IDC_DISABLE);
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while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
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wr_dc_adr (k);
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wr_dc_cst (IDC_LDLCK);
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lines++;
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k += 0x10; /* the number of bytes in a cacheline */
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}
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wr_dc_cst (IDC_UNALL);
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wr_dc_cst (IDC_INVALL);
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if (cacheon)
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wr_dc_cst (IDC_ENABLE);
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else
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wr_dc_cst (IDC_DISABLE);
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return lines << 4;
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};
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/* ------------------------------------------------------------------------- */
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void upmconfig (uint upm, uint * table, uint size)
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{
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uint i;
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uint addr = 0;
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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for (i = 0; i < size; i++) {
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memctl->memc_mdr = table[i]; /* (16-15) */
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memctl->memc_mcr = addr | upm; /* (16-16) */
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addr++;
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}
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}
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/* ------------------------------------------------------------------------- */
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#ifndef CONFIG_LWMON
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong msr, addr;
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
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/* Interrupts and MMU off */
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__asm__ volatile ("mtspr 81, 0");
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__asm__ volatile ("mfmsr %0":"=r" (msr));
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msr &= ~0x1030;
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__asm__ volatile ("mtmsr %0"::"r" (msr));
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/*
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* Trying to execute the next instruction at a non-existing address
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* should cause a machine check, resulting in reset
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*/
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#ifdef CONFIG_SYS_RESET_ADDRESS
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addr = CONFIG_SYS_RESET_ADDRESS;
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#else
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/*
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* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
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* - sizeof (ulong) is usually a valid address. Better pick an address
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* known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
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* "(ulong)-1" used to be a good choice for many systems...
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*/
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addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
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#endif
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((void (*)(void)) addr) ();
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return 1;
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}
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#else /* CONFIG_LWMON */
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/*
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* On the LWMON board, the MCLR reset input of the PIC's on the board
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* uses a 47K/1n RC combination which has a 47us time constant. The
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* low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
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* and thus too short to reset the external hardware. So we use the
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* watchdog to reset the board.
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*/
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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/* prevent triggering the watchdog */
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disable_interrupts ();
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/* make sure the watchdog is running */
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reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
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/* wait for watchdog reset */
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while (1) {};
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/* NOTREACHED */
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return 1;
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|
}
|
|
|
|
#endif /* CONFIG_LWMON */
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
/*
|
|
* Get timebase clock frequency (like cpu_clk in Hz)
|
|
*
|
|
* See sections 14.2 and 14.6 of the User's Manual
|
|
*/
|
|
unsigned long get_tbclk (void)
|
|
{
|
|
uint immr = get_immr (0); /* Return full IMMR contents */
|
|
volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
|
|
ulong oscclk, factor, pll;
|
|
|
|
if (immap->im_clkrst.car_sccr & SCCR_TBS) {
|
|
return (gd->cpu_clk / 16);
|
|
}
|
|
|
|
pll = immap->im_clkrst.car_plprcr;
|
|
|
|
#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
|
|
|
|
/*
|
|
* For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
|
|
* factor is calculated as follows:
|
|
*
|
|
* MFN
|
|
* MFI + -------
|
|
* MFD + 1
|
|
* factor = -----------------
|
|
* (PDF + 1) * 2^S
|
|
*
|
|
* For older chips, it's just MF field of PLPRCR plus one.
|
|
*/
|
|
if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
|
|
factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
|
|
(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
|
|
} else {
|
|
factor = PLPRCR_val(MF)+1;
|
|
}
|
|
|
|
oscclk = gd->cpu_clk / factor;
|
|
|
|
if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
|
|
return (oscclk / 4);
|
|
}
|
|
return (oscclk / 16);
|
|
}
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_WATCHDOG)
|
|
void watchdog_reset (void)
|
|
{
|
|
int re_enable = disable_interrupts ();
|
|
|
|
reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
|
|
if (re_enable)
|
|
enable_interrupts ();
|
|
}
|
|
#endif /* CONFIG_WATCHDOG */
|
|
|
|
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
|
|
|
|
void reset_8xx_watchdog (volatile immap_t * immr)
|
|
{
|
|
# if defined(CONFIG_LWMON)
|
|
/*
|
|
* The LWMON board uses a MAX6301 Watchdog
|
|
* with the trigger pin connected to port PA.7
|
|
*
|
|
* (The old board version used a MAX706TESA Watchdog, which
|
|
* had to be handled exactly the same.)
|
|
*/
|
|
# define WATCHDOG_BIT 0x0100
|
|
immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
|
|
immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
|
|
immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
|
|
|
|
immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
|
|
# elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
|
|
/*
|
|
* The KUP4 boards uses a TPS3705 Watchdog
|
|
* with the trigger pin connected to port PA.5
|
|
*/
|
|
# define WATCHDOG_BIT 0x0400
|
|
immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
|
|
immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
|
|
immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
|
|
|
|
immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
|
|
# else
|
|
/*
|
|
* All other boards use the MPC8xx Internal Watchdog
|
|
*/
|
|
immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
|
|
immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
|
|
# endif /* CONFIG_LWMON */
|
|
}
|
|
#endif /* CONFIG_WATCHDOG */
|
|
|
|
/*
|
|
* Initializes on-chip ethernet controllers.
|
|
* to override, implement board_eth_init()
|
|
*/
|
|
int cpu_eth_init(bd_t *bis)
|
|
{
|
|
#if defined(SCC_ENET) && defined(CONFIG_CMD_NET)
|
|
scc_initialize(bis);
|
|
#endif
|
|
#if defined(FEC_ENET)
|
|
fec_initialize(bis);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|