upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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86 lines
1.6 KiB
86 lines
1.6 KiB
/*
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* Copyright (C) 2015 Panasonic Corporation
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* Copyright (C) 2015 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/err.h>
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#include <usb.h>
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#include <fdtdec.h>
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#include "xhci.h"
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static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int node_list[2];
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fdt_addr_t addr;
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int count;
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count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
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COMPAT_SOCIONEXT_XHCI, node_list,
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ARRAY_SIZE(node_list));
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if (index >= count)
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return -ENODEV;
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addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg");
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if (addr == FDT_ADDR_T_NONE)
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return -ENODEV;
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*base = (struct xhci_hccr *)addr;
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return 0;
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}
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#define USB3_RST_CTRL 0x00100040
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#define IOMMU_RST_N (1 << 5)
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#define LINK_RST_N (1 << 4)
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static void uniphier_xhci_reset(void __iomem *base, int on)
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{
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u32 tmp;
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tmp = readl(base + USB3_RST_CTRL);
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if (on)
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tmp &= ~(IOMMU_RST_N | LINK_RST_N);
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else
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tmp |= IOMMU_RST_N | LINK_RST_N;
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writel(tmp, base + USB3_RST_CTRL);
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}
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
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{
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int ret;
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struct xhci_hccr *cr;
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struct xhci_hcor *or;
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ret = get_uniphier_xhci_base(index, &cr);
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if (ret < 0)
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return ret;
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uniphier_xhci_reset(cr, 0);
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or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
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*hccr = cr;
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*hcor = or;
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return 0;
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}
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void xhci_hcd_stop(int index)
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{
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int ret;
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struct xhci_hccr *cr;
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ret = get_uniphier_xhci_base(index, &cr);
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if (ret < 0)
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return;
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uniphier_xhci_reset(cr, 1);
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}
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