upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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56 lines
1.3 KiB
56 lines
1.3 KiB
/*
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* (C) Copyright 2015 Linaro
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* peter.griffin <peter.griffin@linaro.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dwmmc.h>
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#include <malloc.h>
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#include <linux/errno.h>
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#define DWMMC_MAX_CH_NUM 4
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#define DWMMC_MAX_FREQ 50000000
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#define DWMMC_MIN_FREQ 400000
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/* Source clock is configured to 100MHz by ATF bl1*/
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#define MMC0_DEFAULT_FREQ 100000000
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static int hi6220_dwmci_core_init(struct dwmci_host *host, int index)
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{
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host->name = "Hisilicon DWMMC";
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host->dev_index = index;
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/* Add the mmc channel to be registered with mmc core */
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if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
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printf("DWMMC%d registration failed\n", index);
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return -1;
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}
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return 0;
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}
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/*
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* This function adds the mmc channel to be registered with mmc core.
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* index - mmc channel number.
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* regbase - register base address of mmc channel specified in 'index'.
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* bus_width - operating bus width of mmc channel specified in 'index'.
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*/
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int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width)
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{
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struct dwmci_host *host = NULL;
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host = calloc(1, sizeof(struct dwmci_host));
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if (!host) {
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error("dwmci_host calloc failed!\n");
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return -ENOMEM;
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}
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host->ioaddr = (void *)(ulong)regbase;
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host->buswidth = bus_width;
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host->bus_hz = MMC0_DEFAULT_FREQ;
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return hi6220_dwmci_core_init(host, index);
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}
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