upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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151 lines
3.5 KiB
151 lines
3.5 KiB
/*
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* (C) Copyright 2016
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* Vikas Manocha, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <serial.h>
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#include <asm/arch/stm32.h>
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#include "serial_stm32x7.h"
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DECLARE_GLOBAL_DATA_PTR;
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static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct stm32x7_serial_platdata *plat = dev->platdata;
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struct stm32_usart *const usart = plat->base;
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u32 int_div, mantissa, fraction, oversampling;
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int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
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if (int_div < 16) {
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oversampling = 8;
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setbits_le32(&usart->cr1, USART_CR1_OVER8);
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} else {
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oversampling = 16;
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clrbits_le32(&usart->cr1, USART_CR1_OVER8);
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}
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mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
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fraction = int_div % oversampling;
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writel(mantissa | fraction, &usart->brr);
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return 0;
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}
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static int stm32_serial_getc(struct udevice *dev)
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{
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struct stm32x7_serial_platdata *plat = dev->platdata;
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struct stm32_usart *const usart = plat->base;
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if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
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return -EAGAIN;
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return readl(&usart->rd_dr);
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}
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static int stm32_serial_putc(struct udevice *dev, const char c)
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{
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struct stm32x7_serial_platdata *plat = dev->platdata;
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struct stm32_usart *const usart = plat->base;
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if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
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return -EAGAIN;
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writel(c, &usart->tx_dr);
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return 0;
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}
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static int stm32_serial_pending(struct udevice *dev, bool input)
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{
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struct stm32x7_serial_platdata *plat = dev->platdata;
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struct stm32_usart *const usart = plat->base;
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if (input)
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return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
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else
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return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
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}
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static int stm32_serial_probe(struct udevice *dev)
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{
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struct stm32x7_serial_platdata *plat = dev->platdata;
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struct stm32_usart *const usart = plat->base;
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#ifdef CONFIG_CLK
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int ret;
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struct clk clk;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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#endif
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plat->clock_rate = clk_get_rate(&clk);
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if (plat->clock_rate < 0) {
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clk_disable(&clk);
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return plat->clock_rate;
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};
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/* Disable usart-> disable overrun-> enable usart */
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clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
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setbits_le32(&usart->cr3, USART_CR3_OVRDIS);
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setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
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return 0;
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}
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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static const struct udevice_id stm32_serial_id[] = {
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{.compatible = "st,stm32f7-usart"},
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{.compatible = "st,stm32f7-uart"},
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{.compatible = "st,stm32h7-usart"},
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{.compatible = "st,stm32h7-uart"},
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{}
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};
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static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
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{
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struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
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fdt_addr_t addr;
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addr = devfdt_get_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->base = (struct stm32_usart *)addr;
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return 0;
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}
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#endif
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static const struct dm_serial_ops stm32_serial_ops = {
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.putc = stm32_serial_putc,
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.pending = stm32_serial_pending,
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.getc = stm32_serial_getc,
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.setbrg = stm32_serial_setbrg,
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};
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U_BOOT_DRIVER(serial_stm32) = {
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.name = "serial_stm32x7",
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.id = UCLASS_SERIAL,
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.of_match = of_match_ptr(stm32_serial_id),
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.ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
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.platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
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.ops = &stm32_serial_ops,
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.probe = stm32_serial_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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