upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 
u-boot/drivers/spi/Kconfig

53 lines
1.7 KiB

config DM_SPI
bool "Enable Driver Model for SPI drivers"
depends on DM
help
Enable driver model for SPI. The SPI slave interface
(spi_setup_slave(), spi_xfer(), etc.) is then implemented by
the SPI uclass. Drivers provide methods to access the SPI
buses that they control. The uclass interface is defined in
include/spi.h. The existing spi_slave structure is attached
as 'parent data' to every slave on each bus. Slaves
typically use driver-private data instead of extending the
spi_slave structure.
config SANDBOX_SPI
bool "Sandbox SPI driver"
depends on SANDBOX && DM
help
Enable SPI support for sandbox. This is an emulation of a real SPI
bus. Devices can be attached to the bus using the device tree
which specifies the driver to use. As an example, see this device
tree fragment from sandbox.dts. It shows that the SPI bus has a
single flash device on chip select 0 which is emulated by the driver
for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
spi@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
compatible = "sandbox,spi";
cs-gpios = <0>, <&gpio_a 0>;
flash@0 {
reg = <0>;
compatible = "spansion,m25p16", "sandbox,spi-flash";
spi-max-frequency = <40000000>;
sandbox,filename = "spi.bin";
};
};
config DESIGNWARE_SPI
bool "Designware SPI driver"
depends on DM_SPI
help
Enable the Designware SPI driver. This driver can be used to
access the SPI NOR flash on platforms embedding this Designware
IP core.
config CADENCE_QSPI
bool "Cadence QSPI driver"
depends on DM_SPI
help
Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
used to access the SPI NOR flash on platforms embedding this
Cadence IP core.