upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Trent Piepho a5d212a263 mpc8xxx: LCRR[CLKDIV] is sometimes five bits ... On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>		16 years ago
..
Makefile	FSL DDR: Convert PM854 to new DDR code.	16 years ago
config.mk	…
ddr.c	Pass dimm parameters to populate populate controller options	16 years ago
law.c	rename CFG_ macros to CONFIG_SYS	16 years ago
pm854.c	mpc8xxx: LCRR[CLKDIV] is sometimes five bits	16 years ago
tlb.c	rename CFG_ macros to CONFIG_SYS	16 years ago
u-boot.lds	Align end of bss by 4 bytes	16 years ago