upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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734 lines
21 KiB
734 lines
21 KiB
/*
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* (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
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*
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* (C) Copyright 2006
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* Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
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*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2002,2003, Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <asm/io.h>
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#include <ioports.h>
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#include <flash.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[]; /* FLASH chips info */
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void local_bus_init (void);
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ulong flash_get_size (ulong base, int banknum);
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#ifdef CONFIG_PS2MULT
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void ps2mult_early_init (void);
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#endif
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#ifdef CONFIG_CPM2
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A: conf, ppar, psor, pdir, podr, pdat */
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{
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{1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
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{1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
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{1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
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{1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
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{1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
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{1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
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{0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
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{0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
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{0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
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{0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
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{1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
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{1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
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{1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
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{1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
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{1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
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{1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
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{1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
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{1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
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{0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
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{0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
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{0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
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{0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
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{0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
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{0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
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{0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
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{0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
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{0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
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{0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
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{0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
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{0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
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{0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
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{0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
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},
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/* Port B: conf, ppar, psor, pdir, podr, pdat */
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{
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{1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
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{1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
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{1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
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{1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
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{1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
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{1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
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{1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
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{1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
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{1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
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{1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
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{1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
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{1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
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{1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
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{1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
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{1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
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{1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
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{1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
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{1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
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{1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
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{1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
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{1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
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{1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
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{1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
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{1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
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{1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
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{1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
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{1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
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{1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
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{0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
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},
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/* Port C: conf, ppar, psor, pdir, podr, pdat */
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{
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{0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
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{0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
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{0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
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{0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
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{0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
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{0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
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{0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
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{0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
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{0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
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{0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
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{1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
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{1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
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{1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
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{1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
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{1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
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{1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
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{0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
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{0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
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{0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
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{0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
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{0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
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{0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
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{0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
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{0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
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{0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
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{0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
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{0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
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{0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
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{0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
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{0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
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{0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
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{0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
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},
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/* Port D: conf, ppar, psor, pdir, podr, pdat */
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{
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#ifdef CONFIG_TQM8560
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{1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
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{1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
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{1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
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#else /* !CONFIG_TQM8560 */
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{0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
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{0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
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{0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
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#endif /* CONFIG_TQM8560 */
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{1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
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{1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
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{1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
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{0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
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{0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
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{0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
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{0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
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{0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
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{0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
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{0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
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{0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
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{0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
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{0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
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{0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
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{0, 0, 0, 1, 0, 0}, /* PD14: LED */
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{0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
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{0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
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{0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
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{0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
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{0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
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{0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
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{0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
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{0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
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{0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
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{0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
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{0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
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}
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};
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#endif /* CONFIG_CPM2 */
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#define CASL_STRING1 "casl=xx"
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#define CASL_STRING2 "casl="
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static const int casl_table[] = { 20, 25, 30 };
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#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
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int cas_latency (void)
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{
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char *s = getenv ("serial#");
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int casl;
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int val;
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int i;
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casl = CONFIG_DDR_DEFAULT_CL;
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if (s != NULL) {
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if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
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CASL_STRING2, strlen (CASL_STRING2)) == 0) {
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val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
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for (i = 0; i < N_CASL; ++i) {
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if (val == casl_table[i]) {
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return val;
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}
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}
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}
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}
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return casl;
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}
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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printf ("Board: %s", CONFIG_BOARDNAME);
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if (s != NULL) {
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puts (", serial# ");
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puts (s);
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}
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putc ('\n');
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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return 0;
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}
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int misc_init_r (void)
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{
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volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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/*
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* Adjust flash start and offset to detected values
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*/
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/*
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* Recalculate CS configuration if second FLASH bank is available
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*/
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if (flash_info[0].size > 0) {
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memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
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(CONFIG_SYS_OR1_PRELIM & 0x00007fff);
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memctl->br1 = gd->bd->bi_flashstart |
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(CONFIG_SYS_BR1_PRELIM & 0x00007fff);
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/*
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* Re-check to get correct base address for bank 1
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*/
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flash_get_size (gd->bd->bi_flashstart, 0);
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} else {
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memctl->or1 = 0;
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memctl->br1 = 0;
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}
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/*
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* If bank 1 is equipped, bank 0 is mapped after bank 1
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*/
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memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
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(CONFIG_SYS_OR0_PRELIM & 0x00007fff);
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memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
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(CONFIG_SYS_BR0_PRELIM & 0x00007fff);
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/*
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* Re-check to get correct base address for bank 0
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*/
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flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
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/*
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* Re-do flash protection upon new addresses
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*/
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flash_protect (FLAG_PROTECT_CLEAR,
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gd->bd->bi_flashstart, 0xffffffff,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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|
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/* Monitor protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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|
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/* Environment protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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|
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#ifdef CONFIG_ENV_ADDR_REDUND
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/* Redundant environment protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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#endif
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return 0;
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}
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|
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#ifdef CONFIG_CAN_DRIVER
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/*
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* Initialize UPMC RAM
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*/
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static void upmc_write (u_char addr, uint val)
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{
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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out_be32 (&lbc->mdr, val);
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clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
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MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
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|
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/* dummy access to perform write */
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out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
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/* normal operation */
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clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
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}
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#endif /* CONFIG_CAN_DRIVER */
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uint get_lbc_clock (void)
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{
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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sys_info_t sys_info;
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ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
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get_sys_info (&sys_info);
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if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
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#ifdef CONFIG_MPC8548
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/*
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* Yes, the entire PQ38 family use the same
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* bit-representation for twice the clock divider value.
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|
*/
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clkdiv *= 2;
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#endif
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return sys_info.freqSystemBus / clkdiv;
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}
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puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
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return 0;
|
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}
|
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|
|
/*
|
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* Initialize Local Bus
|
|
*/
|
|
void local_bus_init (void)
|
|
{
|
|
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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|
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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uint lbc_mhz = get_lbc_clock () / 1000000;
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|
|
|
#ifdef CONFIG_MPC8548
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uint svr = get_svr ();
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uint lcrr;
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|
|
|
/*
|
|
* MPC revision < 2.0
|
|
* According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
|
|
* Modify engineering use only register at address 0xE_0F20.
|
|
* "1. Read register at offset 0xE_0F20
|
|
* 2. And value with 0x0000_FFFF
|
|
* 3. OR result with 0x0000_0004
|
|
* 4. Write result back to offset 0xE_0F20."
|
|
*
|
|
* According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
|
|
* Modify engineering use only register at address 0xE_0F20.
|
|
* "1. Read register at offset 0xE_0F20
|
|
* 2. And value with 0xFFFF_FFDF
|
|
* 3. Write result back to offset 0xE_0F20."
|
|
*
|
|
* Since it is the same register, we do the modification in one step.
|
|
*/
|
|
if (SVR_MAJ (svr) < 2) {
|
|
uint dummy = gur->lbiuiplldcr1;
|
|
dummy &= 0x0000FFDF;
|
|
dummy |= 0x00000004;
|
|
gur->lbiuiplldcr1 = dummy;
|
|
}
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|
|
|
lcrr = CONFIG_SYS_LBC_LCRR;
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|
|
|
/*
|
|
* Local Bus Clock > 83.3 MHz. According to timing
|
|
* specifications set LCRR[EADC] to 2 delay cycles.
|
|
*/
|
|
if (lbc_mhz > 83) {
|
|
lcrr &= ~LCRR_EADC;
|
|
lcrr |= LCRR_EADC_2;
|
|
}
|
|
|
|
/*
|
|
* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
|
|
* disable PLL bypass for Local Bus Clock > 83 MHz.
|
|
*/
|
|
if (lbc_mhz >= 66)
|
|
lcrr &= (~LCRR_DBYP); /* DLL Enabled */
|
|
|
|
else
|
|
lcrr |= LCRR_DBYP; /* DLL Bypass */
|
|
|
|
lbc->lcrr = lcrr;
|
|
asm ("sync;isync;msync");
|
|
|
|
/*
|
|
* According to MPC8548ERMAD Rev.1.3 read back LCRR
|
|
* and terminate with isync
|
|
*/
|
|
lcrr = lbc->lcrr;
|
|
asm ("isync;");
|
|
|
|
/* let DLL stabilize */
|
|
udelay (500);
|
|
|
|
#else /* !CONFIG_MPC8548 */
|
|
|
|
/*
|
|
* Errata LBC11.
|
|
* Fix Local Bus clock glitch when DLL is enabled.
|
|
*
|
|
* If localbus freq is < 66MHz, DLL bypass mode must be used.
|
|
* If localbus freq is > 133MHz, DLL can be safely enabled.
|
|
* Between 66 and 133, the DLL is enabled with an override workaround.
|
|
*/
|
|
|
|
if (lbc_mhz < 66) {
|
|
lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
|
|
lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
|
|
LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */
|
|
|
|
} else if (lbc_mhz >= 133) {
|
|
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
|
|
|
|
} else {
|
|
/*
|
|
* On REV1 boards, need to change CLKDIV before enable DLL.
|
|
* Default CLKDIV is 8, change it to 4 temporarily.
|
|
*/
|
|
uint pvr = get_pvr ();
|
|
uint temp_lbcdll = 0;
|
|
|
|
if (pvr == PVR_85xx_REV1) {
|
|
/* FIXME: Justify the high bit here. */
|
|
lbc->lcrr = 0x10000004;
|
|
}
|
|
|
|
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
|
|
udelay (200);
|
|
|
|
/*
|
|
* Sample LBC DLL ctrl reg, upshift it to set the
|
|
* override bits.
|
|
*/
|
|
temp_lbcdll = gur->lbcdllcr;
|
|
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
|
|
asm ("sync;isync;msync");
|
|
}
|
|
#endif /* !CONFIG_MPC8548 */
|
|
|
|
#ifdef CONFIG_CAN_DRIVER
|
|
/*
|
|
* According to timing specifications EAD must be
|
|
* set if Local Bus Clock is > 83 MHz.
|
|
*/
|
|
if (lbc_mhz > 83)
|
|
out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
|
|
else
|
|
out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
|
|
out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
|
|
|
|
/* LGPL4 is UPWAIT */
|
|
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
|
|
|
|
/* Initialize UPMC for CAN: single read */
|
|
upmc_write (0x00, 0xFFFFED00);
|
|
upmc_write (0x01, 0xCCFFCC00);
|
|
upmc_write (0x02, 0x00FFCF00);
|
|
upmc_write (0x03, 0x00FFCF00);
|
|
upmc_write (0x04, 0x00FFDC00);
|
|
upmc_write (0x05, 0x00FFCF00);
|
|
upmc_write (0x06, 0x00FFED00);
|
|
upmc_write (0x07, 0x3FFFCC07);
|
|
|
|
/* Initialize UPMC for CAN: single write */
|
|
upmc_write (0x18, 0xFFFFED00);
|
|
upmc_write (0x19, 0xCCFFEC00);
|
|
upmc_write (0x1A, 0x00FFED80);
|
|
upmc_write (0x1B, 0x00FFED80);
|
|
upmc_write (0x1C, 0x00FFFC00);
|
|
upmc_write (0x1D, 0x0FFFEC00);
|
|
upmc_write (0x1E, 0x0FFFEF00);
|
|
upmc_write (0x1F, 0x3FFFEC05);
|
|
#endif /* CONFIG_CAN_DRIVER */
|
|
}
|
|
|
|
/*
|
|
* Initialize PCI Devices, report devices found.
|
|
*/
|
|
static int first_free_busno;
|
|
|
|
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
|
|
extern void fsl_pci_init(struct pci_controller *hose);
|
|
|
|
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
|
|
static struct pci_controller pci1_hose;
|
|
#endif /* CONFIG_PCI || CONFIG_PCI1 */
|
|
|
|
#ifdef CONFIG_PCIE1
|
|
static struct pci_controller pcie1_hose;
|
|
#endif /* CONFIG_PCIE1 */
|
|
|
|
static inline void init_pci1(void)
|
|
{
|
|
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
|
|
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
|
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
|
|
struct pci_controller *hose = &pci1_hose;
|
|
struct pci_region *r = hose->regions;
|
|
|
|
/* PORDEVSR[15] */
|
|
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
|
|
/* PORDEVSR[14] */
|
|
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
|
|
/* PORPLLSR[16] */
|
|
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
|
|
|
|
uint pci_agent = (host_agent == 3) || (host_agent == 4 ) ||
|
|
(host_agent == 6);
|
|
|
|
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
|
|
|
|
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
|
|
printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n",
|
|
(pci_32) ? 32 : 64,
|
|
(pci_speed == 33333333) ? "33" :
|
|
(pci_speed == 66666666) ? "66" : "unknown",
|
|
pci_clk_sel ? "sync" : "async",
|
|
pci_agent ? "agent" : "host",
|
|
pci_arb ? "arbiter" : "external-arbiter");
|
|
|
|
|
|
/* inbound */
|
|
r += fsl_pci_setup_inbound_windows(r);
|
|
|
|
/* outbound memory */
|
|
pci_set_region (r++,
|
|
CONFIG_SYS_PCI1_MEM_BASE,
|
|
CONFIG_SYS_PCI1_MEM_PHYS,
|
|
CONFIG_SYS_PCI1_MEM_SIZE,
|
|
PCI_REGION_MEM);
|
|
|
|
/* outbound io */
|
|
pci_set_region (r++,
|
|
CONFIG_SYS_PCI1_IO_BASE,
|
|
CONFIG_SYS_PCI1_IO_PHYS,
|
|
CONFIG_SYS_PCI1_IO_SIZE,
|
|
PCI_REGION_IO);
|
|
|
|
hose->region_count = r - hose->regions;
|
|
|
|
hose->first_busno = first_free_busno;
|
|
pci_setup_indirect (hose, (int)&pci->cfg_addr,
|
|
(int)&pci->cfg_data);
|
|
|
|
fsl_pci_init (hose);
|
|
|
|
printf (" PCI on bus %02x..%02x\n",
|
|
hose->first_busno, hose->last_busno);
|
|
|
|
first_free_busno = hose->last_busno + 1;
|
|
#ifdef CONFIG_PCIX_CHECK
|
|
if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
|
|
ushort reg16 =
|
|
PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
|
|
PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
|
|
uint dev = PCI_BDF(hose->first_busno, 0, 0);
|
|
|
|
/* PCI-X init */
|
|
if (CONFIG_SYS_CLK_FREQ < 66000000)
|
|
puts ("PCI-X will only work at 66 MHz\n");
|
|
|
|
pci_hose_write_config_word (hose, dev, PCIX_COMMAND,
|
|
reg16);
|
|
}
|
|
#endif
|
|
} else {
|
|
puts ("PCI1: disabled\n");
|
|
}
|
|
#else /* !(CONFIG_PCI || CONFIG_PCI1) */
|
|
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
|
|
#endif /* CONFIG_PCI || CONFIG_PCI1) */
|
|
}
|
|
|
|
static inline void init_pcie1(void)
|
|
{
|
|
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
#ifdef CONFIG_PCIE1
|
|
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
|
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
|
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
|
|
struct pci_controller *hose = &pcie1_hose;
|
|
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) ||
|
|
(host_agent == 3);
|
|
struct pci_region *r = hose->regions;
|
|
|
|
int pcie_configured = io_sel >= 1;
|
|
|
|
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
|
|
printf ("PCIe: %s, base address %x",
|
|
pcie_ep ? "End point" : "Root complex", (uint)pci);
|
|
|
|
if (pci->pme_msg_det) {
|
|
pci->pme_msg_det = 0xffffffff;
|
|
debug (", with errors. Clearing. Now 0x%08x",
|
|
pci->pme_msg_det);
|
|
}
|
|
puts ("\n");
|
|
|
|
/* inbound */
|
|
r += fsl_pci_setup_inbound_windows(r);
|
|
|
|
/* outbound memory */
|
|
pci_set_region (r++,
|
|
CONFIG_SYS_PCIE1_MEM_BASE,
|
|
CONFIG_SYS_PCIE1_MEM_PHYS,
|
|
CONFIG_SYS_PCIE1_MEM_SIZE,
|
|
PCI_REGION_MEM);
|
|
|
|
/* outbound io */
|
|
pci_set_region (r++,
|
|
CONFIG_SYS_PCIE1_IO_BASE,
|
|
CONFIG_SYS_PCIE1_IO_PHYS,
|
|
CONFIG_SYS_PCIE1_IO_SIZE,
|
|
PCI_REGION_IO);
|
|
|
|
hose->region_count = r - hose->regions;
|
|
|
|
hose->first_busno = first_free_busno;
|
|
pci_setup_indirect(hose, (int)&pci->cfg_addr,
|
|
(int)&pci->cfg_data);
|
|
|
|
fsl_pci_init (hose);
|
|
printf (" PCIe on bus %02x..%02x\n",
|
|
hose->first_busno, hose->last_busno);
|
|
|
|
first_free_busno = hose->last_busno + 1;
|
|
|
|
} else {
|
|
printf ("PCIe: disabled\n");
|
|
}
|
|
#else /* !CONFIG_PCIE1 */
|
|
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
|
|
#endif /* CONFIG_PCIE1 */
|
|
}
|
|
|
|
void pci_init_board (void)
|
|
{
|
|
init_pci1();
|
|
init_pcie1();
|
|
}
|
|
|
|
#ifdef CONFIG_OF_BOARD_SETUP
|
|
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
|
struct pci_controller *hose);
|
|
|
|
void ft_board_setup (void *blob, bd_t *bd)
|
|
{
|
|
ft_cpu_setup (blob, bd);
|
|
|
|
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
|
|
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
|
#endif
|
|
#ifdef CONFIG_PCIE1
|
|
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
|
|
#endif
|
|
}
|
|
#endif /* CONFIG_OF_BOARD_SETUP */
|
|
|
|
#ifdef CONFIG_BOARD_EARLY_INIT_R
|
|
int board_early_init_r (void)
|
|
{
|
|
#ifdef CONFIG_PS2MULT
|
|
ps2mult_early_init ();
|
|
#endif /* CONFIG_PS2MULT */
|
|
return (0);
|
|
}
|
|
#endif /* CONFIG_BOARD_EARLY_INIT_R */
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
cpu_eth_init(bis); /* Intialize TSECs first */
|
|
return pci_eth_init(bis);
|
|
}
|
|
|