upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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329 lines
8.9 KiB
329 lines
8.9 KiB
/*
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* (C) Copyright 2004-2009
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* Texas Instruments Incorporated
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* Richard Woodruff <r-woodruff2@ti.com>
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* Aneesh V <aneesh@ti.com>
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* Balaji Krishnamoorthy <balajitk@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MUX_OMAP4_H_
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#define _MUX_OMAP4_H_
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#include <asm/types.h>
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struct pad_conf_entry {
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u16 offset;
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u16 val;
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};
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#ifdef CONFIG_OFF_PADCONF
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#define OFF_PD (1 << 12)
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#define OFF_PU (3 << 12)
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#define OFF_OUT_PTD (0 << 10)
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#define OFF_OUT_PTU (2 << 10)
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#define OFF_IN (1 << 10)
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#define OFF_OUT (0 << 10)
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#define OFF_EN (1 << 9)
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#else
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#define OFF_PD (0 << 12)
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#define OFF_PU (0 << 12)
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#define OFF_OUT_PTD (0 << 10)
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#define OFF_OUT_PTU (0 << 10)
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#define OFF_IN (0 << 10)
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#define OFF_OUT (0 << 10)
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#define OFF_EN (0 << 9)
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#endif
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#define IEN (1 << 8)
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#define IDIS (0 << 8)
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#define PTU (3 << 3)
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#define PTD (1 << 3)
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#define EN (1 << 3)
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#define DIS (0 << 3)
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#define M0 0
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#define M1 1
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#define M2 2
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#define M3 3
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#define M4 4
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#define M5 5
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#define M6 6
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#define M7 7
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#define SAFE_MODE M7
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#ifdef CONFIG_OFF_PADCONF
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#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
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#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
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#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
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#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
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#else
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#define OFF_IN_PD 0
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#define OFF_IN_PU 0
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#define OFF_OUT_PD 0
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#define OFF_OUT_PU 0
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#endif
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#define CORE_REVISION 0x0000
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#define CORE_HWINFO 0x0004
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#define CORE_SYSCONFIG 0x0010
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#define GPMC_AD0 0x0040
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#define GPMC_AD1 0x0042
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#define GPMC_AD2 0x0044
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#define GPMC_AD3 0x0046
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#define GPMC_AD4 0x0048
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#define GPMC_AD5 0x004A
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#define GPMC_AD6 0x004C
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#define GPMC_AD7 0x004E
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#define GPMC_AD8 0x0050
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#define GPMC_AD9 0x0052
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#define GPMC_AD10 0x0054
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#define GPMC_AD11 0x0056
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#define GPMC_AD12 0x0058
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#define GPMC_AD13 0x005A
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#define GPMC_AD14 0x005C
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#define GPMC_AD15 0x005E
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#define GPMC_A16 0x0060
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#define GPMC_A17 0x0062
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#define GPMC_A18 0x0064
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#define GPMC_A19 0x0066
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#define GPMC_A20 0x0068
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#define GPMC_A21 0x006A
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#define GPMC_A22 0x006C
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#define GPMC_A23 0x006E
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#define GPMC_A24 0x0070
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#define GPMC_A25 0x0072
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#define GPMC_NCS0 0x0074
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#define GPMC_NCS1 0x0076
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#define GPMC_NCS2 0x0078
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#define GPMC_NCS3 0x007A
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#define GPMC_NWP 0x007C
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#define GPMC_CLK 0x007E
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#define GPMC_NADV_ALE 0x0080
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#define GPMC_NOE 0x0082
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#define GPMC_NWE 0x0084
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#define GPMC_NBE0_CLE 0x0086
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#define GPMC_NBE1 0x0088
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#define GPMC_WAIT0 0x008A
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#define GPMC_WAIT1 0x008C
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#define C2C_DATA11 0x008E
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#define C2C_DATA12 0x0090
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#define C2C_DATA13 0x0092
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#define C2C_DATA14 0x0094
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#define C2C_DATA15 0x0096
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#define HDMI_HPD 0x0098
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#define HDMI_CEC 0x009A
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#define HDMI_DDC_SCL 0x009C
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#define HDMI_DDC_SDA 0x009E
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#define CSI21_DX0 0x00A0
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#define CSI21_DY0 0x00A2
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#define CSI21_DX1 0x00A4
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#define CSI21_DY1 0x00A6
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#define CSI21_DX2 0x00A8
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#define CSI21_DY2 0x00AA
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#define CSI21_DX3 0x00AC
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#define CSI21_DY3 0x00AE
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#define CSI21_DX4 0x00B0
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#define CSI21_DY4 0x00B2
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#define CSI22_DX0 0x00B4
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#define CSI22_DY0 0x00B6
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#define CSI22_DX1 0x00B8
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#define CSI22_DY1 0x00BA
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#define CAM_SHUTTER 0x00BC
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#define CAM_STROBE 0x00BE
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#define CAM_GLOBALRESET 0x00C0
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#define USBB1_ULPITLL_CLK 0x00C2
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#define USBB1_ULPITLL_STP 0x00C4
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#define USBB1_ULPITLL_DIR 0x00C6
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#define USBB1_ULPITLL_NXT 0x00C8
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#define USBB1_ULPITLL_DAT0 0x00CA
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#define USBB1_ULPITLL_DAT1 0x00CC
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#define USBB1_ULPITLL_DAT2 0x00CE
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#define USBB1_ULPITLL_DAT3 0x00D0
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#define USBB1_ULPITLL_DAT4 0x00D2
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#define USBB1_ULPITLL_DAT5 0x00D4
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#define USBB1_ULPITLL_DAT6 0x00D6
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#define USBB1_ULPITLL_DAT7 0x00D8
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#define USBB1_HSIC_DATA 0x00DA
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#define USBB1_HSIC_STROBE 0x00DC
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#define USBC1_ICUSB_DP 0x00DE
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#define USBC1_ICUSB_DM 0x00E0
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#define SDMMC1_CLK 0x00E2
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#define SDMMC1_CMD 0x00E4
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#define SDMMC1_DAT0 0x00E6
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#define SDMMC1_DAT1 0x00E8
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#define SDMMC1_DAT2 0x00EA
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#define SDMMC1_DAT3 0x00EC
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#define SDMMC1_DAT4 0x00EE
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#define SDMMC1_DAT5 0x00F0
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#define SDMMC1_DAT6 0x00F2
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#define SDMMC1_DAT7 0x00F4
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#define ABE_MCBSP2_CLKX 0x00F6
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#define ABE_MCBSP2_DR 0x00F8
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#define ABE_MCBSP2_DX 0x00FA
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#define ABE_MCBSP2_FSX 0x00FC
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#define ABE_MCBSP1_CLKX 0x00FE
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#define ABE_MCBSP1_DR 0x0100
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#define ABE_MCBSP1_DX 0x0102
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#define ABE_MCBSP1_FSX 0x0104
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#define ABE_PDM_UL_DATA 0x0106
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#define ABE_PDM_DL_DATA 0x0108
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#define ABE_PDM_FRAME 0x010A
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#define ABE_PDM_LB_CLK 0x010C
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#define ABE_CLKS 0x010E
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#define ABE_DMIC_CLK1 0x0110
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#define ABE_DMIC_DIN1 0x0112
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#define ABE_DMIC_DIN2 0x0114
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#define ABE_DMIC_DIN3 0x0116
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#define UART2_CTS 0x0118
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#define UART2_RTS 0x011A
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#define UART2_RX 0x011C
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#define UART2_TX 0x011E
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#define HDQ_SIO 0x0120
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#define I2C1_SCL 0x0122
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#define I2C1_SDA 0x0124
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#define I2C2_SCL 0x0126
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#define I2C2_SDA 0x0128
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#define I2C3_SCL 0x012A
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#define I2C3_SDA 0x012C
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#define I2C4_SCL 0x012E
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#define I2C4_SDA 0x0130
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#define MCSPI1_CLK 0x0132
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#define MCSPI1_SOMI 0x0134
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#define MCSPI1_SIMO 0x0136
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#define MCSPI1_CS0 0x0138
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#define MCSPI1_CS1 0x013A
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#define MCSPI1_CS2 0x013C
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#define MCSPI1_CS3 0x013E
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#define UART3_CTS_RCTX 0x0140
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#define UART3_RTS_SD 0x0142
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#define UART3_RX_IRRX 0x0144
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#define UART3_TX_IRTX 0x0146
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#define SDMMC5_CLK 0x0148
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#define SDMMC5_CMD 0x014A
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#define SDMMC5_DAT0 0x014C
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#define SDMMC5_DAT1 0x014E
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#define SDMMC5_DAT2 0x0150
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#define SDMMC5_DAT3 0x0152
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#define MCSPI4_CLK 0x0154
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#define MCSPI4_SIMO 0x0156
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#define MCSPI4_SOMI 0x0158
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#define MCSPI4_CS0 0x015A
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#define UART4_RX 0x015C
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#define UART4_TX 0x015E
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#define USBB2_ULPITLL_CLK 0x0160
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#define USBB2_ULPITLL_STP 0x0162
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#define USBB2_ULPITLL_DIR 0x0164
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#define USBB2_ULPITLL_NXT 0x0166
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#define USBB2_ULPITLL_DAT0 0x0168
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#define USBB2_ULPITLL_DAT1 0x016A
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#define USBB2_ULPITLL_DAT2 0x016C
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#define USBB2_ULPITLL_DAT3 0x016E
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#define USBB2_ULPITLL_DAT4 0x0170
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#define USBB2_ULPITLL_DAT5 0x0172
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#define USBB2_ULPITLL_DAT6 0x0174
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#define USBB2_ULPITLL_DAT7 0x0176
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#define USBB2_HSIC_DATA 0x0178
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#define USBB2_HSIC_STROBE 0x017A
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#define UNIPRO_TX0 0x017C
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#define UNIPRO_TY0 0x017E
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#define UNIPRO_TX1 0x0180
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#define UNIPRO_TY1 0x0182
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#define UNIPRO_TX2 0x0184
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#define UNIPRO_TY2 0x0186
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#define UNIPRO_RX0 0x0188
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#define UNIPRO_RY0 0x018A
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#define UNIPRO_RX1 0x018C
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#define UNIPRO_RY1 0x018E
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#define UNIPRO_RX2 0x0190
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#define UNIPRO_RY2 0x0192
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#define USBA0_OTG_CE 0x0194
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#define USBA0_OTG_DP 0x0196
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#define USBA0_OTG_DM 0x0198
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#define FREF_CLK1_OUT 0x019A
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#define FREF_CLK2_OUT 0x019C
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#define SYS_NIRQ1 0x019E
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#define SYS_NIRQ2 0x01A0
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#define SYS_BOOT0 0x01A2
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#define SYS_BOOT1 0x01A4
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#define SYS_BOOT2 0x01A6
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#define SYS_BOOT3 0x01A8
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#define SYS_BOOT4 0x01AA
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#define SYS_BOOT5 0x01AC
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#define DPM_EMU0 0x01AE
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#define DPM_EMU1 0x01B0
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#define DPM_EMU2 0x01B2
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#define DPM_EMU3 0x01B4
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#define DPM_EMU4 0x01B6
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#define DPM_EMU5 0x01B8
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#define DPM_EMU6 0x01BA
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#define DPM_EMU7 0x01BC
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#define DPM_EMU8 0x01BE
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#define DPM_EMU9 0x01C0
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#define DPM_EMU10 0x01C2
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#define DPM_EMU11 0x01C4
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#define DPM_EMU12 0x01C6
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#define DPM_EMU13 0x01C8
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#define DPM_EMU14 0x01CA
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#define DPM_EMU15 0x01CC
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#define DPM_EMU16 0x01CE
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#define DPM_EMU17 0x01D0
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#define DPM_EMU18 0x01D2
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#define DPM_EMU19 0x01D4
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#define WAKEUPEVENT_0 0x01D8
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#define WAKEUPEVENT_1 0x01DC
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#define WAKEUPEVENT_2 0x01E0
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#define WAKEUPEVENT_3 0x01E4
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#define WAKEUPEVENT_4 0x01E8
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#define WAKEUPEVENT_5 0x01EC
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#define WAKEUPEVENT_6 0x01F0
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#define WKUP_REVISION 0x0000
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#define WKUP_HWINFO 0x0004
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#define WKUP_SYSCONFIG 0x0010
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#define PAD0_SIM_IO 0x0040
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#define PAD1_SIM_CLK 0x0042
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#define PAD0_SIM_RESET 0x0044
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#define PAD1_SIM_CD 0x0046
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#define PAD0_SIM_PWRCTRL 0x0048
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#define PAD1_SR_SCL 0x004A
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#define PAD0_SR_SDA 0x004C
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#define PAD1_FREF_XTAL_IN 0x004E
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#define PAD0_FREF_SLICER_IN 0x0050
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#define PAD1_FREF_CLK_IOREQ 0x0052
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#define PAD0_FREF_CLK0_OUT 0x0054
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#define PAD1_FREF_CLK3_REQ 0x0056
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#define PAD0_FREF_CLK3_OUT 0x0058
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#define PAD1_FREF_CLK4_REQ 0x005A
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#define PAD0_FREF_CLK4_OUT 0x005C
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#define PAD1_SYS_32K 0x005E
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#define PAD0_SYS_NRESPWRON 0x0060
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#define PAD1_SYS_NRESWARM 0x0062
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#define PAD0_SYS_PWR_REQ 0x0064
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#define PAD1_SYS_PWRON_RESET 0x0066
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#define PAD0_SYS_BOOT6 0x0068
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#define PAD1_SYS_BOOT7 0x006A
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#define PAD0_JTAG_NTRST 0x006C
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#define PAD1_JTAG_TCK 0x006D
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#define PAD0_JTAG_RTCK 0x0070
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#define PAD1_JTAG_TMS_TMSC 0x0072
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#define PAD0_JTAG_TDI 0x0074
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#define PAD1_JTAG_TDO 0x0076
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#define PADCONF_WAKEUPEVENT_0 0x007C
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#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0
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#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4
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#define PADCONF_MODE 0x05A8
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#define CONTROL_XTAL_OSCILLATOR 0x05AC
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#define CONTROL_CONTROL_I2C_2 0x0604
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#define CONTROL_CONTROL_JTAG 0x0608
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#define CONTROL_CONTROL_SYS 0x060C
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#define CONTROL_SPARE_RW 0x0614
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#define CONTROL_SPARE_R 0x0618
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#define CONTROL_SPARE_R_C0 0x061C
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#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A
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#endif /* _MUX_OMAP4_H_ */
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