upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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260 lines
9.8 KiB
260 lines
9.8 KiB
/**
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* @file IxDmaAcc.h
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*
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* @date 15 October 2002
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*
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* @brief API of the IXP400 DMA Access Driver Component (IxDma)
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/*---------------------------------------------------------------------
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Doxygen group definitions
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---------------------------------------------------------------------*/
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#ifndef IXDMAACC_H
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#define IXDMAACC_H
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#include "IxOsal.h"
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#include "IxNpeDl.h"
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/**
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* @defgroup IxDmaTypes IXP400 DMA Types (IxDmaTypes)
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* @brief The common set of types used in the DMA component
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* @{
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*/
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/**
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* @ingroup IxDmaTypes
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* @enum IxDmaReturnStatus
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* @brief Dma return status definitions
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*/
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typedef enum
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{
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IX_DMA_SUCCESS = IX_SUCCESS, /**< DMA Transfer Success */
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IX_DMA_FAIL = IX_FAIL, /**< DMA Transfer Fail */
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IX_DMA_INVALID_TRANSFER_WIDTH, /**< Invalid transfer width */
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IX_DMA_INVALID_TRANSFER_LENGTH, /**< Invalid transfer length */
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IX_DMA_INVALID_TRANSFER_MODE, /**< Invalid transfer mode */
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IX_DMA_INVALID_ADDRESS_MODE, /**< Invalid address mode */
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IX_DMA_REQUEST_FIFO_FULL /**< DMA request queue is full */
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} IxDmaReturnStatus;
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/**
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* @ingroup IxDmaTypes
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* @enum IxDmaTransferMode
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* @brief Dma transfer mode definitions
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* @note Copy and byte swap, and copy and reverse modes only support multiples of word data length.
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*/
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typedef enum
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{
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IX_DMA_COPY_CLEAR = 0, /**< copy and clear source*/
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IX_DMA_COPY, /**< copy */
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IX_DMA_COPY_BYTE_SWAP, /**< copy and byte swap (endian) */
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IX_DMA_COPY_REVERSE, /**< copy and reverse */
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IX_DMA_TRANSFER_MODE_INVALID /**< Invalid transfer mode */
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} IxDmaTransferMode;
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/**
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* @ingroup IxDmaTypes
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* @enum IxDmaAddressingMode
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* @brief Dma addressing mode definitions
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* @note Fixed source address to fixed destination address addressing mode is not supported.
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*/
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typedef enum
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{
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IX_DMA_INC_SRC_INC_DST = 0, /**< Incremental source address to incremental destination address */
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IX_DMA_INC_SRC_FIX_DST, /**< Incremental source address to incremental destination address */
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IX_DMA_FIX_SRC_INC_DST, /**< Incremental source address to incremental destination address */
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IX_DMA_FIX_SRC_FIX_DST, /**< Incremental source address to incremental destination address */
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IX_DMA_ADDRESSING_MODE_INVALID /**< Invalid Addressing Mode */
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} IxDmaAddressingMode;
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/**
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* @ingroup IxDmaTypes
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* @enum IxDmaTransferWidth
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* @brief Dma transfer width definitions
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* @Note Fixed addresses (either source or destination) do not support burst transfer width.
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*/
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typedef enum
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{
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IX_DMA_32_SRC_32_DST = 0, /**< 32-bit src to 32-bit dst */
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IX_DMA_32_SRC_16_DST, /**< 32-bit src to 16-bit dst */
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IX_DMA_32_SRC_8_DST, /**< 32-bit src to 8-bit dst */
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IX_DMA_16_SRC_32_DST, /**< 16-bit src to 32-bit dst */
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IX_DMA_16_SRC_16_DST, /**< 16-bit src to 16-bit dst */
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IX_DMA_16_SRC_8_DST, /**< 16-bit src to 8-bit dst */
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IX_DMA_8_SRC_32_DST, /**< 8-bit src to 32-bit dst */
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IX_DMA_8_SRC_16_DST, /**< 8-bit src to 16-bit dst */
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IX_DMA_8_SRC_8_DST, /**< 8-bit src to 8-bit dst */
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IX_DMA_8_SRC_BURST_DST, /**< 8-bit src to burst dst - Not supported for fixed destination address */
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IX_DMA_16_SRC_BURST_DST, /**< 16-bit src to burst dst - Not supported for fixed destination address */
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IX_DMA_32_SRC_BURST_DST, /**< 32-bit src to burst dst - Not supported for fixed destination address */
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IX_DMA_BURST_SRC_8_DST, /**< burst src to 8-bit dst - Not supported for fixed source address */
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IX_DMA_BURST_SRC_16_DST, /**< burst src to 16-bit dst - Not supported for fixed source address */
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IX_DMA_BURST_SRC_32_DST, /**< burst src to 32-bit dst - Not supported for fixed source address*/
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IX_DMA_BURST_SRC_BURST_DST, /**< burst src to burst dst - Not supported for fixed source and destination address
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*/
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IX_DMA_TRANSFER_WIDTH_INVALID /**< Invalid transfer width */
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} IxDmaTransferWidth;
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/**
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* @ingroup IxDmaTypes
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* @enum IxDmaNpeId
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* @brief NpeId numbers to identify NPE A, B or C
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*/
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typedef enum
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{
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IX_DMA_NPEID_NPEA = 0, /**< Identifies NPE A */
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IX_DMA_NPEID_NPEB, /**< Identifies NPE B */
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IX_DMA_NPEID_NPEC, /**< Identifies NPE C */
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IX_DMA_NPEID_MAX /**< Total Number of NPEs */
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} IxDmaNpeId;
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/* @} */
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/**
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* @defgroup IxDmaAcc IXP400 DMA Access Driver (IxDmaAcc) API
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*
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* @brief The public API for the IXP400 IxDmaAcc component
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*
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* @{
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*/
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/**
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* @ingroup IxDmaAcc
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* @brief DMA Request Id type
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*/
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typedef UINT32 IxDmaAccRequestId;
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/**
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* @ingroup IxDmaAcc
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* @def IX_DMA_REQUEST_FULL
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* @brief DMA request queue is full
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* This constant is a return value used to tell the user that the IxDmaAcc
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* queue is full.
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*
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*/
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#define IX_DMA_REQUEST_FULL 16
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/**
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* @ingroup IxDmaAcc
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* @brief DMA completion notification
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* This function is called to notify a client that the DMA has been completed
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* @param status @ref IxDmaReturnStatus [out] - reporting to client
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*
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*/
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typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status);
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/**
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* @ingroup IxDmaAcc
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*
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* @fn ixDmaAccInit(IxNpeDlNpeId npeId)
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*
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* @brief Initialise the DMA Access component
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* This function will initialise the DMA Access component internals
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* @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer
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* @return @li IX_SUCCESS succesfully initialised the component
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* @return @li IX_FAIL Initialisation failed for some unspecified
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* internal reason.
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*/
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PUBLIC IX_STATUS
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ixDmaAccInit(IxNpeDlNpeId npeId);
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/**
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* @ingroup IxDmaAcc
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*
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* @fn ixDmaAccDmaTransfer(
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IxDmaAccDmaCompleteCallback callback,
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UINT32 SourceAddr,
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UINT32 DestinationAddr,
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UINT16 TransferLength,
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IxDmaTransferMode TransferMode,
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IxDmaAddressingMode AddressingMode,
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IxDmaTransferWidth TransferWidth)
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*
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* @brief Perform DMA transfer
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* This function will perform DMA transfer between devices within the
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* IXP400 memory map.
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* @note The following are restrictions for IxDmaAccDmaTransfer:
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* @li The function is non re-entrant.
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* @li The function assumes host devices are operating in big-endian mode.
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* @li Fixed address does not suport burst transfer width
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* @li Fixed source address to fixed destinatiom address mode is not suported
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* @li The incrementing source address for expansion bus will not support a burst transfer width and copy and clear mode
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*
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* @param callback @ref IxDmaAccDmaCompleteCallback [in] - function pointer to be stored and called when the DMA transfer is completed. This cannot be NULL.
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* @param SourceAddr UINT32 [in] - Starting address of DMA source. Must be a valid IXP400 memory map address.
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* @param DestinationAddr UINT32 [in] - Starting address of DMA destination. Must be a valid IXP400 memory map address.
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* @param TransferLength UINT16 [in] - The size of DMA data transfer. The range must be from 1-64Kbyte
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* @param TransferMode @ref IxDmaTransferMode [in] - The DMA transfer mode
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* @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode
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* @param TransferWidth @ref IxDmaTransferWidth [in] - The DMA transfer width
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*
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* @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful
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* @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured
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* @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid
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* @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range
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* @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid
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* @return @li IX_DMA_REQUEST_FIFO_FULL IxDmaAcc request queue is full
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*/
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PUBLIC IxDmaReturnStatus
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ixDmaAccDmaTransfer(
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IxDmaAccDmaCompleteCallback callback,
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UINT32 SourceAddr,
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UINT32 DestinationAddr,
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UINT16 TransferLength,
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IxDmaTransferMode TransferMode,
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IxDmaAddressingMode AddressingMode,
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IxDmaTransferWidth TransferWidth);
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/**
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* @ingroup IxDmaAcc
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*
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* @fn ixDmaAccShow(void)
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*
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* @brief Display some component information for debug purposes
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* Show some internal operation information relating to the DMA service.
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* At a minimum the following will show.
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* - the number of the DMA pend (in queue)
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* @param None
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* @return @li None
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*/
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PUBLIC IX_STATUS
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ixDmaAccShow(void);
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#endif /* IXDMAACC_H */
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