upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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807 lines
19 KiB
807 lines
19 KiB
/*
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* (C) Copyright 2001
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2001-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <linux/byteorder/swab.h>
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/* Board support for 1 or 2 flash devices */
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#define FLASH_PORT_WIDTH8
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typedef unsigned char FLASH_PORT_WIDTH;
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typedef volatile unsigned char FLASH_PORT_WIDTHV;
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#define SWAP(x) (x)
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/* Intel-compatible flash ID */
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#define INTEL_COMPAT 0x89
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#define INTEL_ALT 0xB0
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/* Intel-compatible flash commands */
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#define INTEL_PROGRAM 0x10
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#define INTEL_ERASE 0x20
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#define INTEL_CLEAR 0x50
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#define INTEL_LOCKBIT 0x60
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#define INTEL_PROTECT 0x01
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#define INTEL_STATUS 0x70
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#define INTEL_READID 0x90
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#define INTEL_CONFIRM 0xD0
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#define INTEL_RESET 0xFF
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/* Intel-compatible flash status bits */
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#define INTEL_FINISHED 0x80
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#define INTEL_OK 0x80
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define FLASH_CYCLE1 0x0555
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#define FLASH_CYCLE2 0x02aa
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#define WR_BLOCK 0x20
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (FPW * addr, flash_info_t * info);
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static int write_data (flash_info_t * info, ulong dest, FPW data);
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static int write_data_block (flash_info_t * info, ulong src, ulong dest);
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static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
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static void flash_get_offsets (ulong base, flash_info_t * info);
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void inline spin_wheel (void);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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int i;
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ulong size = 0;
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ulong fsize = 0;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
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memset (&flash_info[i], 0, sizeof (flash_info_t));
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switch (i) {
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case 0:
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flash_get_size ((FPW *) CFG_FLASH1_BASE,
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&flash_info[i]);
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flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]);
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break;
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case 1:
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flash_get_size ((FPW *) CFG_FLASH1_BASE,
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&flash_info[i]);
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fsize = CFG_FLASH1_BASE + flash_info[i - 1].size;
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flash_get_offsets (fsize, &flash_info[i]);
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break;
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case 2:
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flash_get_size ((FPW *) CFG_FLASH0_BASE,
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&flash_info[i]);
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flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]);
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break;
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case 3:
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flash_get_size ((FPW *) CFG_FLASH0_BASE,
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&flash_info[i]);
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fsize = CFG_FLASH0_BASE + flash_info[i - 1].size;
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flash_get_offsets (fsize, &flash_info[i]);
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break;
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default:
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panic ("configured to many flash banks!\n");
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break;
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}
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size += flash_info[i].size;
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}
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/* Protect monitor and environment sectors
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*/
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#if defined (CFG_AMD_BOOT)
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flash_protect (FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[2]);
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flash_protect (FLAG_PROTECT_SET,
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CFG_INTEL_BASE,
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CFG_INTEL_BASE + monitor_flash_len - 1,
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&flash_info[1]);
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#else
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flash_protect (FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[3]);
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flash_protect (FLAG_PROTECT_SET,
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CFG_AMD_BASE,
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CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
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#endif
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flash_protect (FLAG_PROTECT_SET,
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CFG_ENV1_ADDR,
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CFG_ENV1_ADDR + CFG_ENV1_SIZE - 1, &flash_info[1]);
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flash_protect (FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[3]);
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return size;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t * info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN)
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return;
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
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for (i = 0; i < info->sector_count; i++) {
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info->start[i] = base + (i * PHYS_AMD_SECT_SIZE);
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info->protect[i] = 0;
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}
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}
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
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for (i = 0; i < info->sector_count; i++) {
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info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
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info->protect[i] = 0;
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}
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}
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t * info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_INTEL:
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printf ("INTEL ");
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break;
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case FLASH_MAN_AMD:
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printf ("AMD ");
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break;
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default:
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printf ("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_28F128J3A:
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printf ("28F128J3A\n");
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break;
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case FLASH_AM040:
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printf ("AMD29F040B\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i], info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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return;
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}
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size (FPW * addr, flash_info_t * info)
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{
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FPWV value;
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static int amd = 0;
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/* Write auto select command: read Manufacturer ID */
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/* Write auto select command sequence and test FLASH answer */
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addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
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__asm__ ("sync");
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addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
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__asm__ ("sync");
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addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */
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__asm__ ("sync");
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udelay (100);
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switch (addr[0] & 0xff) {
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case (uchar) AMD_MANUFACT:
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info->flash_id = FLASH_MAN_AMD;
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value = addr[1];
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break;
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case (uchar) INTEL_MANUFACT:
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info->flash_id = FLASH_MAN_INTEL;
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value = addr[2];
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break;
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default:
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printf ("unknown\n");
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
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return (0); /* no or unknown flash */
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}
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switch (value) {
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case (FPW) INTEL_ID_28F128J3A:
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info->flash_id += FLASH_28F128J3A;
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info->sector_count = 64;
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info->size = 0x00800000; /* => 16 MB */
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break;
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case (FPW) AMD_ID_LV040B:
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info->flash_id += FLASH_AM040;
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if (amd == 0) {
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info->sector_count = 7;
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info->size = 0x00070000; /* => 448 KB */
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amd = 1;
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} else {
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/* for Environment settings */
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info->sector_count = 1;
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info->size = PHYS_AMD_SECT_SIZE; /* => 64 KB */
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amd = 0;
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}
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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break;
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}
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if (info->sector_count > CFG_MAX_FLASH_SECT) {
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printf ("** ERROR: sector count %d > max (%d) **\n",
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info->sector_count, CFG_MAX_FLASH_SECT);
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info->sector_count = CFG_MAX_FLASH_SECT;
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}
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if (value == (FPW) INTEL_ID_28F128J3A)
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
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else
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addr[0] = (FPW) 0x00F000F0; /* restore read mode */
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return (info->size);
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t * info, int s_first, int s_last)
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{
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int flag, prot, sect;
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ulong type, start, last;
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int rcode = 0, intel = 0;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN)
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printf ("- missing\n");
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else
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printf ("- no sectors to erase\n");
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return 1;
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}
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type = (info->flash_id & FLASH_VENDMASK);
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if ((type != FLASH_MAN_INTEL)) {
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type = (info->flash_id & FLASH_VENDMASK);
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if ((type != FLASH_MAN_AMD)) {
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printf ("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return 1;
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}
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}
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if (type == FLASH_MAN_INTEL)
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intel = 1;
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n", prot);
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} else {
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printf ("\n");
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}
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start = get_timer (0);
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last = start;
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts ();
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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FPWV *addr = (FPWV *) (info->start[sect]);
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FPW status;
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printf ("Erasing sector %2d ... ", sect);
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/* arm simple, non interrupt dependent timer */
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start = get_timer (0);
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if (intel) {
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*addr = (FPW) 0x00500050; /* clear status register */
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*addr = (FPW) 0x00200020; /* erase setup */
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*addr = (FPW) 0x00D000D0; /* erase confirm */
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} else {
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FPWV *base; /* first address in bank */
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base = (FPWV *) (CFG_AMD_BASE);
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base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
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base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
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base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
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base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
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base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
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*addr = (FPW) 0x00300030; /* erase sector */
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}
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while (((status =
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*addr) & (FPW) 0x00800080) !=
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(FPW) 0x00800080) {
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if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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if (intel) {
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*addr = (FPW) 0x00B000B0; /* suspend erase */
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*addr = (FPW) 0x00FF00FF; /* reset to read mode */
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} else
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*addr = (FPW) 0x00F000F0; /* reset to read mode */
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rcode = 1;
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break;
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}
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}
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if (intel) {
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*addr = (FPW) 0x00500050; /* clear status register cmd. */
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*addr = (FPW) 0x00FF00FF; /* resest to read mode */
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} else
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*addr = (FPW) 0x00F000F0; /* reset to read mode */
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printf (" done\n");
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}
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}
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return rcode;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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* 4 - Flash not identified
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*/
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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{
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if (info->flash_id == FLASH_UNKNOWN) {
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return 4;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD:
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{
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FPW data = 0; /* 16 or 32 bit word, matches flash bus width */
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int bytes; /* number of bytes to program in current word */
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int left; /* number of bytes left to program */
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int i, res;
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for (left = cnt, res = 0;
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left > 0 && res == 0;
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addr += sizeof (data), left -=
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sizeof (data) - bytes) {
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bytes = addr & (sizeof (data) - 1);
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addr &= ~(sizeof (data) - 1);
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/* combine source and destination data so can program
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* an entire word of 16 or 32 bits
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*/
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for (i = 0; i < sizeof (data); i++) {
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data <<= 8;
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if (i < bytes || i - bytes >= left)
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data += *((uchar *) addr + i);
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else
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data += *src++;
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}
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res = write_word_amd (info, (FPWV *) addr,
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data);
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}
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return res;
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} /* case FLASH_MAN_AMD */
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case FLASH_MAN_INTEL:
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{
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ulong cp, wp;
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FPW data;
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int count, i, l, rc, port_width;
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/* get lower word aligned address */
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wp = addr;
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port_width = 1;
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/*
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* handle unaligned start bytes
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*/
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if ((l = addr - wp) != 0) {
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data = 0;
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for (i = 0, cp = wp; i < l; ++i, ++cp) {
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data = (data << 8) | (*(uchar *) cp);
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}
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for (; i < port_width && cnt > 0; ++i) {
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data = (data << 8) | *src++;
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--cnt;
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++cp;
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}
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for (; cnt == 0 && i < port_width; ++i, ++cp)
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data = (data << 8) | (*(uchar *) cp);
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|
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if ((rc =
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write_data (info, wp, SWAP (data))) != 0)
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return (rc);
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wp += port_width;
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}
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|
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if (cnt > WR_BLOCK) {
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/*
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* handle word aligned part
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*/
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count = 0;
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while (cnt >= WR_BLOCK) {
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|
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if ((rc =
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write_data_block (info,
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(ulong) src,
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wp)) != 0)
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return (rc);
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wp += WR_BLOCK;
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src += WR_BLOCK;
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cnt -= WR_BLOCK;
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|
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if (count++ > 0x800) {
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spin_wheel ();
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count = 0;
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}
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}
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}
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|
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if (cnt < WR_BLOCK) {
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/*
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* handle word aligned part
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*/
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count = 0;
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while (cnt >= port_width) {
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data = 0;
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for (i = 0; i < port_width; ++i)
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data = (data << 8) | *src++;
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|
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if ((rc =
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write_data (info, wp,
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SWAP (data))) != 0)
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return (rc);
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|
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wp += port_width;
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cnt -= port_width;
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if (count++ > 0x800) {
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spin_wheel ();
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count = 0;
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|
}
|
|
}
|
|
}
|
|
|
|
if (cnt == 0)
|
|
return (0);
|
|
|
|
/*
|
|
* handle unaligned tail bytes
|
|
*/
|
|
data = 0;
|
|
for (i = 0, cp = wp; i < port_width && cnt > 0;
|
|
++i, ++cp) {
|
|
data = (data << 8) | *src++;
|
|
--cnt;
|
|
}
|
|
|
|
for (; i < port_width; ++i, ++cp)
|
|
data = (data << 8) | (*(uchar *) cp);
|
|
|
|
return (write_data (info, wp, SWAP (data)));
|
|
} /* case FLASH_MAN_INTEL */
|
|
|
|
} /* switch */
|
|
return (0);
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Write a word or halfword to Flash, returns:
|
|
* 0 - OK
|
|
* 1 - write timeout
|
|
* 2 - Flash not erased
|
|
*/
|
|
static int write_data (flash_info_t * info, ulong dest, FPW data)
|
|
{
|
|
FPWV *addr = (FPWV *) dest;
|
|
ulong start;
|
|
int flag;
|
|
|
|
/* Check if Flash is (sufficiently) erased */
|
|
if ((*addr & data) != data) {
|
|
printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
|
|
return (2);
|
|
}
|
|
/* Disable interrupts which might cause a timeout here */
|
|
flag = disable_interrupts ();
|
|
|
|
*addr = (FPW) 0x00400040; /* write setup */
|
|
*addr = data;
|
|
|
|
/* arm simple, non interrupt dependent timer */
|
|
start = get_timer (0);
|
|
|
|
/* wait while polling the status register */
|
|
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
|
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
|
|
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
|
return (1);
|
|
}
|
|
}
|
|
|
|
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Write a word or halfword to Flash, returns:
|
|
* 0 - OK
|
|
* 1 - write timeout
|
|
* 2 - Flash not erased
|
|
*/
|
|
static int write_data_block (flash_info_t * info, ulong src, ulong dest)
|
|
{
|
|
FPWV *srcaddr = (FPWV *) src;
|
|
FPWV *dstaddr = (FPWV *) dest;
|
|
ulong start;
|
|
int flag, i;
|
|
|
|
/* Check if Flash is (sufficiently) erased */
|
|
for (i = 0; i < WR_BLOCK; i++)
|
|
if ((*dstaddr++ & 0xff) != 0xff) {
|
|
printf ("not erased at %08lx (%lx)\n",
|
|
(ulong) dstaddr, *dstaddr);
|
|
return (2);
|
|
}
|
|
|
|
dstaddr = (FPWV *) dest;
|
|
|
|
/* Disable interrupts which might cause a timeout here */
|
|
flag = disable_interrupts ();
|
|
|
|
*dstaddr = (FPW) 0x00e800e8; /* write block setup */
|
|
|
|
/* arm simple, non interrupt dependent timer */
|
|
start = get_timer (0);
|
|
|
|
/* wait while polling the status register */
|
|
while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
|
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
|
|
*dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
|
|
return (1);
|
|
}
|
|
}
|
|
|
|
*dstaddr = (FPW) 0x001f001f; /* write 32 to buffer */
|
|
for (i = 0; i < WR_BLOCK; i++)
|
|
*dstaddr++ = *srcaddr++;
|
|
|
|
dstaddr -= 1;
|
|
*dstaddr = (FPW) 0x00d000d0; /* write 32 to buffer */
|
|
|
|
/* arm simple, non interrupt dependent timer */
|
|
start = get_timer (0);
|
|
|
|
/* wait while polling the status register */
|
|
while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
|
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
|
|
*dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
|
|
return (1);
|
|
}
|
|
}
|
|
|
|
*dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Write a word to Flash for AMD FLASH
|
|
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
|
* (not an individual chip) is.
|
|
*
|
|
* returns:
|
|
* 0 - OK
|
|
* 1 - write timeout
|
|
* 2 - Flash not erased
|
|
*/
|
|
static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
|
|
{
|
|
ulong start;
|
|
int flag;
|
|
int res = 0; /* result, assume success */
|
|
FPWV *base; /* first address in flash bank */
|
|
|
|
/* Check if Flash is (sufficiently) erased */
|
|
if ((*dest & data) != data) {
|
|
return (2);
|
|
}
|
|
|
|
base = (FPWV *) (CFG_AMD_BASE);
|
|
|
|
/* Disable interrupts which might cause a timeout here */
|
|
flag = disable_interrupts ();
|
|
|
|
base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
|
|
base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
|
|
base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */
|
|
|
|
*dest = data; /* start programming the data */
|
|
|
|
/* re-enable interrupts if necessary */
|
|
if (flag)
|
|
enable_interrupts ();
|
|
|
|
start = get_timer (0);
|
|
|
|
/* data polling for D7 */
|
|
while (res == 0
|
|
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
|
|
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
|
|
*dest = (FPW) 0x00F000F0; /* reset bank */
|
|
res = 1;
|
|
}
|
|
}
|
|
|
|
return (res);
|
|
}
|
|
|
|
void inline spin_wheel (void)
|
|
{
|
|
static int p = 0;
|
|
static char w[] = "\\/-";
|
|
|
|
printf ("\010%c", w[p]);
|
|
(++p == 3) ? (p = 0) : 0;
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Set/Clear sector's lock bit, returns:
|
|
* 0 - OK
|
|
* 1 - Error (timeout, voltage problems, etc.)
|
|
*/
|
|
int flash_real_protect (flash_info_t * info, long sector, int prot)
|
|
{
|
|
ulong start;
|
|
int i;
|
|
int rc = 0;
|
|
FPWV *addr = (FPWV *) (info->start[sector]);
|
|
int flag = disable_interrupts ();
|
|
|
|
/*
|
|
* 29F040B AMD flash does not support software protection/unprotection,
|
|
* the only way to protect the AMD flash is marked it as prot bit.
|
|
* This flash only support hardware protection, by supply or not supply
|
|
* 12vpp to the flash
|
|
*/
|
|
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
|
|
info->protect[sector] = prot;
|
|
|
|
return 0;
|
|
}
|
|
|
|
*addr = INTEL_CLEAR; /* Clear status register */
|
|
if (prot) { /* Set sector lock bit */
|
|
*addr = INTEL_LOCKBIT; /* Sector lock bit */
|
|
*addr = INTEL_PROTECT; /* set */
|
|
} else { /* Clear sector lock bit */
|
|
*addr = INTEL_LOCKBIT; /* All sectors lock bits */
|
|
*addr = INTEL_CONFIRM; /* clear */
|
|
}
|
|
|
|
start = get_timer (0);
|
|
|
|
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
|
|
if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) {
|
|
printf ("Flash lock bit operation timed out\n");
|
|
rc = 1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (*addr != INTEL_OK) {
|
|
printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
|
|
(uint) addr, (uint) * addr);
|
|
rc = 1;
|
|
}
|
|
|
|
if (!rc)
|
|
info->protect[sector] = prot;
|
|
|
|
/*
|
|
* Clear lock bit command clears all sectors lock bits, so
|
|
* we have to restore lock bits of protected sectors.
|
|
*/
|
|
if (!prot) {
|
|
for (i = 0; i < info->sector_count; i++) {
|
|
if (info->protect[i]) {
|
|
start = get_timer (0);
|
|
addr = (FPWV *) (info->start[i]);
|
|
*addr = INTEL_LOCKBIT; /* Sector lock bit */
|
|
*addr = INTEL_PROTECT; /* set */
|
|
while ((*addr & INTEL_FINISHED) !=
|
|
INTEL_FINISHED) {
|
|
if (get_timer (start) >
|
|
CFG_FLASH_UNLOCK_TOUT) {
|
|
printf ("Flash lock bit operation timed out\n");
|
|
rc = 1;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (flag)
|
|
enable_interrupts ();
|
|
|
|
*addr = INTEL_RESET; /* Reset to read array mode */
|
|
|
|
return rc;
|
|
}
|
|
|