upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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203 lines
4.0 KiB
203 lines
4.0 KiB
/*
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* Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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* 02111-1307, USA.
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*
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/imx-regs.h>
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.globl memsetup
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memsetup:
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mov r10, lr
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/* Change PERCLK1DIV to 14 ie 14+1 */
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ldr r0, =PCDR
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ldr r1, =CFG_PCDR_VAL
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str r1, [r0]
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/* set MCU PLL Control Register 0 */
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ldr r0, =MPCTL0
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ldr r1, =CFG_MPCTL0_VAL
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str r1, [r0]
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/* set mpll restart bit */
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ldr r0, =CSCR
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ldr r1, [r0]
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orr r1,r1,#(1<<21)
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str r1, [r0]
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mov r2,#0x10
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1:
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mov r3,#0x2000
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2:
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subs r3,r3,#1
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bne 2b
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subs r2,r2,#1
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bne 1b
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/* set System PLL Control Register 0 */
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ldr r0, =SPCTL0
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ldr r1, =CFG_SPCTL0_VAL
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str r1, [r0]
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/* set spll restart bit */
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ldr r0, =CSCR
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ldr r1, [r0]
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orr r1,r1,#(1<<22)
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str r1, [r0]
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mov r2,#0x10
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1:
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mov r3,#0x2000
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2:
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subs r3,r3,#1
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bne 2b
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subs r2,r2,#1
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bne 1b
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ldr r0, =CSCR
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ldr r1, =CFG_CSCR_VAL
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str r1, [r0]
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/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
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*this.....
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*
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* It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
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* register 1, this stops it using the output of the PLL and thus runs at the
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* slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
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* use the value set in the CM_OSC registers...regardless of what you set it
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* too! Thus, although i thought i was running at 140MHz, i'm actually running
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* at 40!..
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* Slapping this into my bootloader does the trick...
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* MRC p15,0,r0,c1,c0,0 ; read core configuration register
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* ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
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* MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
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* register
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*/
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MRC p15,0,r0,c1,c0,0
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ORR r0,r0,#0xC0000000
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MCR p15,0,r0,c1,c0,0
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ldr r0, =GPR(0)
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ldr r1, =CFG_GPR_A_VAL
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str r1, [r0]
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ldr r0, =GIUS(0)
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ldr r1, =CFG_GIUS_A_VAL
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str r1, [r0]
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/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
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ldr r0, =FMCR
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ldr r1, =CFG_FMCR_VAL
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str r1, [r0]
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ldr r0, =CS0U
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ldr r1, =CFG_CS0U_VAL
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str r1, [r0]
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ldr r0, =CS0L
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ldr r1, =CFG_CS0L_VAL
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str r1, [r0]
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ldr r0, =CS1U
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ldr r1, =CFG_CS1U_VAL
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str r1, [r0]
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ldr r0, =CS1L
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ldr r1, =CFG_CS1L_VAL
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str r1, [r0]
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ldr r0, =CS2U
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ldr r1, =CFG_CS2U_VAL
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str r1, [r0]
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ldr r0, =CS2L
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ldr r1, =CFG_CS2L_VAL
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str r1, [r0]
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ldr r0, =CS3U
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ldr r1, =CFG_CS3U_VAL
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str r1, [r0]
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ldr r0, =CS3L
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ldr r1, =CFG_CS3L_VAL
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str r1, [r0]
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ldr r0, =CS4U
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ldr r1, =CFG_CS4U_VAL
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str r1, [r0]
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ldr r0, =CS4L
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ldr r1, =CFG_CS4L_VAL
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str r1, [r0]
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ldr r0, =CS5U
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ldr r1, =CFG_CS5U_VAL
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str r1, [r0]
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ldr r0, =CS5L
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ldr r1, =CFG_CS5L_VAL
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str r1, [r0]
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/* SDRAM Setup */
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ldr r0, =SDCTL0
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ldr r1, =PRECHARGE_CMD
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str r1, [r0]
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ldr r0, =0x08200000
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ldr r1, =0x0 /* Issue Precharge all Command */
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str r1, [r0]
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ldr r0, =SDCTL0
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ldr r1, =AUTOREFRESH_CMD
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str r1, [r0]
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ldr r0, =0x08000000
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ldr r1, =0x0 /* Issue AutoRefresh Command */
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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ldr r0, =SDCTL0
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ldr r1, =0xb10a8300
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str r1, [r0]
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ldr r0, =0x08223000 /* CAS Latency 2 */
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ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
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str r1, [r0]
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ldr r0, =SDCTL0
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ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
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str r1, [r0]
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mov pc,r10
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