upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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264 lines
7.1 KiB
264 lines
7.1 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <405gp_enet.h>
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#include <asm/processor.h>
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#include <ppc4xx.h>
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#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
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#ifdef CFG_INIT_DCACHE_CS
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# if (CFG_INIT_DCACHE_CS == 0)
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# define PBxAP pb0ap
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# define PBxCR pb0cr
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# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
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# define PBxAP_VAL CFG_EBC_PB0AP
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# define PBxCR_VAL CFG_EBC_PB0CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 1)
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# define PBxAP pb1ap
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# define PBxCR pb1cr
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# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
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# define PBxAP_VAL CFG_EBC_PB1AP
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# define PBxCR_VAL CFG_EBC_PB1CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 2)
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# define PBxAP pb2ap
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# define PBxCR pb2cr
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# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
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# define PBxAP_VAL CFG_EBC_PB2AP
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# define PBxCR_VAL CFG_EBC_PB2CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 3)
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# define PBxAP pb3ap
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# define PBxCR pb3cr
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# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
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# define PBxAP_VAL CFG_EBC_PB3AP
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# define PBxCR_VAL CFG_EBC_PB3CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 4)
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# define PBxAP pb4ap
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# define PBxCR pb4cr
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# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
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# define PBxAP_VAL CFG_EBC_PB4AP
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# define PBxCR_VAL CFG_EBC_PB4CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 5)
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# define PBxAP pb5ap
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# define PBxCR pb5cr
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# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
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# define PBxAP_VAL CFG_EBC_PB5AP
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# define PBxCR_VAL CFG_EBC_PB5CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 6)
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# define PBxAP pb6ap
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# define PBxCR pb6cr
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# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
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# define PBxAP_VAL CFG_EBC_PB6AP
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# define PBxCR_VAL CFG_EBC_PB6CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 7)
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# define PBxAP pb7ap
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# define PBxCR pb7cr
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# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
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# define PBxAP_VAL CFG_EBC_PB7AP
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# define PBxCR_VAL CFG_EBC_PB7CR
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# endif
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# endif
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#endif /* CFG_INIT_DCACHE_CS */
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers
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*/
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void
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cpu_init_f (void)
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{
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#if defined(CONFIG_405EP)
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/*
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* GPIO0 setup (select GPIO or alternate function)
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*/
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out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
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out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
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out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
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out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
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out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
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out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
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out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
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/*
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* Set EMAC noise filter bits
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*/
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mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
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#endif /* CONFIG_405EP */
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/*
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* External Bus Controller (EBC) Setup
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*/
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#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
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/*
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* Move the next instructions into icache, since these modify the flash
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* we are running from!
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*/
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asm volatile(" bl 0f" ::: "lr");
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asm volatile("0: mflr 3" ::: "r3");
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asm volatile(" addi 4, 0, 14" ::: "r4");
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asm volatile(" mtctr 4" ::: "ctr");
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asm volatile("1: icbt 0, 3");
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asm volatile(" addi 3, 3, 32" ::: "r3");
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asm volatile(" bdnz 1b" ::: "ctr", "cr0");
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asm volatile(" addis 3, 0, 0x0" ::: "r3");
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asm volatile(" ori 3, 3, 0xA000" ::: "r3");
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asm volatile(" mtctr 3" ::: "ctr");
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asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
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mtebc(pb0ap, CFG_EBC_PB0AP);
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mtebc(pb0cr, CFG_EBC_PB0CR);
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#endif
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#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
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mtebc(pb1ap, CFG_EBC_PB1AP);
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mtebc(pb1cr, CFG_EBC_PB1CR);
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#endif
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#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
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mtebc(pb2ap, CFG_EBC_PB2AP);
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mtebc(pb2cr, CFG_EBC_PB2CR);
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#endif
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#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
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mtebc(pb3ap, CFG_EBC_PB3AP);
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mtebc(pb3cr, CFG_EBC_PB3CR);
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#endif
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#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
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mtebc(pb4ap, CFG_EBC_PB4AP);
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mtebc(pb4cr, CFG_EBC_PB4CR);
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#endif
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#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
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mtebc(pb5ap, CFG_EBC_PB5AP);
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mtebc(pb5cr, CFG_EBC_PB5CR);
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#endif
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#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
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mtebc(pb6ap, CFG_EBC_PB6AP);
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mtebc(pb6cr, CFG_EBC_PB6CR);
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#endif
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#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
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mtebc(pb7ap, CFG_EBC_PB7AP);
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mtebc(pb7cr, CFG_EBC_PB7CR);
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#endif
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#if defined(CONFIG_WATCHDOG)
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unsigned long val;
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val = mfspr(tcr);
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val |= 0xf0000000; /* generate system reset after 2.684 seconds */
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mtspr(tcr, val);
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val = mfspr(tsr);
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val |= 0x80000000; /* enable watchdog timer */
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mtspr(tsr, val);
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reset_4xx_watchdog();
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#endif /* CONFIG_WATCHDOG */
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}
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/*
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* initialize higher level parts of CPU like time base and timers
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*/
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int cpu_init_r (void)
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{
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#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
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DECLARE_GLOBAL_DATA_PTR;
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bd_t *bd = gd->bd;
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unsigned long reg;
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#if defined(CONFIG_405GP)
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uint pvr = get_pvr();
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#endif
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#ifdef CFG_INIT_DCACHE_CS
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/*
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* Flush and invalidate dcache, then disable CS for temporary stack.
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* Afterwards, this CS can be used for other purposes
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*/
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dcache_disable(); /* flush and invalidate dcache */
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mtebc(PBxAP, 0);
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mtebc(PBxCR, 0); /* disable CS for temporary stack */
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#if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
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/*
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* Write new value into CS register
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*/
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mtebc(PBxAP, PBxAP_VAL);
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mtebc(PBxCR, PBxCR_VAL);
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#endif
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#endif /* CFG_INIT_DCACHE_CS */
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/*
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* Write Ethernetaddress into on-chip register
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*/
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reg = 0x00000000;
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reg |= bd->bi_enetaddr[0]; /* set high address */
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reg = reg << 8;
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reg |= bd->bi_enetaddr[1];
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out32 (EMAC_IAH, reg);
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reg = 0x00000000;
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reg |= bd->bi_enetaddr[2]; /* set low address */
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reg = reg << 8;
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reg |= bd->bi_enetaddr[3];
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reg = reg << 8;
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reg |= bd->bi_enetaddr[4];
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reg = reg << 8;
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reg |= bd->bi_enetaddr[5];
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out32 (EMAC_IAL, reg);
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#if defined(CONFIG_405GP)
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/*
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* Set edge conditioning circuitry on PPC405GPr
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* for compatibility to existing PPC405GP designs.
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*/
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if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
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mtdcr(ecr, 0x60606000);
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}
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#endif /* defined(CONFIG_405GP) */
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#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
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return (0);
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}
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