upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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286 lines
7.6 KiB
286 lines
7.6 KiB
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/*
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* PCI Configuration space access support for MPC83xx PCI Bridge
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*/
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <common.h>
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#include <pci.h>
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#include <i2c.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <fdt_support.h>
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#endif
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#include <asm/fsl_i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_PCI)
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#define PCI_FUNCTION_CONFIG 0x44
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#define PCI_FUNCTION_CFG_LOCK 0x20
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/*
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* Initialize PCI Devices, report devices found
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc83xxemds_config_table[] = {
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{
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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pci_cfgfunc_config_device,
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{PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
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},
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{}
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}
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#endif
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static struct pci_controller hose[] = {
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc83xxemds_config_table,
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#endif
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},
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};
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/**********************************************************************
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* pci_init_board()
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*********************************************************************/
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void pci_init_board(void)
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#ifdef CONFIG_PCISLAVE
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{
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u16 reg16;
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volatile immap_t *immr;
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volatile law83xx_t *pci_law;
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volatile pot83xx_t *pci_pot;
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volatile pcictrl83xx_t *pci_ctrl;
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volatile pciconf83xx_t *pci_conf;
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immr = (immap_t *) CONFIG_SYS_IMMR;
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pci_law = immr->sysconf.pcilaw;
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pci_pot = immr->ios.pot;
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pci_ctrl = immr->pci_ctrl;
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pci_conf = immr->pci_conf;
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/*
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* Configure PCI Inbound Translation Windows
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*/
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pci_ctrl[0].pitar0 = 0x0;
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pci_ctrl[0].pibar0 = 0x0;
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pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
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PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
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pci_ctrl[0].pitar1 = 0x0;
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pci_ctrl[0].pibar1 = 0x0;
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pci_ctrl[0].piebar1 = 0x0;
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pci_ctrl[0].piwar1 &= ~PIWAR_EN;
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pci_ctrl[0].pitar2 = 0x0;
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pci_ctrl[0].pibar2 = 0x0;
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pci_ctrl[0].piebar2 = 0x0;
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pci_ctrl[0].piwar2 &= ~PIWAR_EN;
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hose[0].first_busno = 0;
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hose[0].last_busno = 0xff;
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pci_setup_indirect(&hose[0],
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(CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
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reg16 = 0xff;
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pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
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PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
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PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
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PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
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PCI_LATENCY_TIMER, 0x80);
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/*
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* Unlock configuration lock in PCI function configuration register.
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*/
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pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
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PCI_FUNCTION_CONFIG, ®16);
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reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
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pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
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PCI_FUNCTION_CONFIG, reg16);
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printf("Enabled PCI 32bit Agent Mode\n");
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}
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#else
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{
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volatile immap_t *immr;
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volatile clk83xx_t *clk;
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volatile law83xx_t *pci_law;
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volatile pot83xx_t *pci_pot;
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volatile pcictrl83xx_t *pci_ctrl;
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volatile pciconf83xx_t *pci_conf;
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u16 reg16;
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u32 val32;
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u32 dev;
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immr = (immap_t *) CONFIG_SYS_IMMR;
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clk = (clk83xx_t *) & immr->clk;
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pci_law = immr->sysconf.pcilaw;
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pci_pot = immr->ios.pot;
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pci_ctrl = immr->pci_ctrl;
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pci_conf = immr->pci_conf;
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/*
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* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
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*/
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val32 = clk->occr;
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udelay(2000);
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#if defined(PCI_66M)
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clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
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printf("PCI clock is 66MHz\n");
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#elif defined(PCI_33M)
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clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
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OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
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printf("PCI clock is 33MHz\n");
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#else
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clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
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printf("PCI clock is 66MHz\n");
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#endif
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udelay(2000);
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/*
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* Configure PCI Local Access Windows
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*/
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pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
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pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
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/*
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* Configure PCI Outbound Translation Windows
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*/
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/* PCI mem space - prefetch */
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pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[0].pocmr =
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POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
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/* PCI mmio - non-prefetch mem space */
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pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
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/* PCI IO space */
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pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
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/*
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* Configure PCI Inbound Translation Windows
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*/
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pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
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pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
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pci_ctrl[0].piebar1 = 0x0;
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pci_ctrl[0].piwar1 =
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PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
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PIWAR_IWS_2G;
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/*
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* Release PCI RST Output signal
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*/
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udelay(2000);
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pci_ctrl[0].gcr = 1;
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udelay(2000);
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hose[0].first_busno = 0;
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hose[0].last_busno = 0xff;
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/* PCI memory prefetch space */
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pci_set_region(hose[0].regions + 0,
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CONFIG_SYS_PCI_MEM_BASE,
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CONFIG_SYS_PCI_MEM_PHYS,
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CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
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/* PCI memory space */
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pci_set_region(hose[0].regions + 1,
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CONFIG_SYS_PCI_MMIO_BASE,
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CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose[0].regions + 2,
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CONFIG_SYS_PCI_IO_BASE,
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CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
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/* System memory space */
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pci_set_region(hose[0].regions + 3,
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CONFIG_SYS_PCI_SLV_MEM_LOCAL,
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CONFIG_SYS_PCI_SLV_MEM_BUS,
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CONFIG_SYS_PCI_SLV_MEM_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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hose[0].region_count = 4;
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pci_setup_indirect(&hose[0],
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(CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
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pci_register_hose(hose);
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/*
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* Write command register
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*/
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reg16 = 0xff;
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dev = PCI_BDF(0, 0, 0);
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pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
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/*
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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}
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#endif /* CONFIG_PCISLAVE */
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#if defined(CONFIG_OF_LIBFDT)
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void ft_pci_setup(void *blob, bd_t *bd)
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{
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int nodeoffset;
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int tmp[2];
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const char *path;
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nodeoffset = fdt_path_offset(blob, "/aliases");
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if (nodeoffset >= 0) {
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path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
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if (path) {
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tmp[0] = cpu_to_be32(hose[0].first_busno);
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tmp[1] = cpu_to_be32(hose[0].last_busno);
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do_fixup_by_path(blob, path, "bus-range",
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&tmp, sizeof(tmp), 1);
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tmp[0] = cpu_to_be32(gd->pci_clk);
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do_fixup_by_path(blob, path, "clock-frequency",
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&tmp, sizeof(tmp[0]), 1);
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}
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}
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}
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#endif /* CONFIG_OF_LIBFDT */
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#endif /* CONFIG_PCI */
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