upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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81 lines
1.4 KiB
81 lines
1.4 KiB
/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/uart.h>
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#include <asm/arch-rockchip/grf_rk3036.h>
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#include <asm/arch/sdram_rk3036.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_BASE 0x20008000
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void get_ddr_config(struct rk3036_ddr_config *config)
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{
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/* K4B4G1646Q config */
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config->ddr_type = 3;
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config->rank = 1;
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config->cs0_row = 15;
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config->cs1_row = 15;
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/* 8bank */
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config->bank = 3;
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config->col = 10;
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/* 16bit bw */
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config->bw = 1;
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}
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#define FASTBOOT_KEY_GPIO 93
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int fastboot_key_pressed(void)
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{
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gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
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gpio_direction_input(FASTBOOT_KEY_GPIO);
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return !gpio_get_value(FASTBOOT_KEY_GPIO);
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}
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#define ROCKCHIP_BOOT_MODE_FASTBOOT 0x5242C309
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int board_late_init(void)
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{
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struct rk3036_grf * const grf = (void *)GRF_BASE;
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int boot_mode = readl(&grf->os_reg[4]);
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/* Clear boot mode */
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writel(0, &grf->os_reg[4]);
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if (boot_mode == ROCKCHIP_BOOT_MODE_FASTBOOT ||
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fastboot_key_pressed()) {
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printf("enter fastboot!\n");
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setenv("preboot", "setenv preboot; fastboot usb0");
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}
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = sdram_size();
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return 0;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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