upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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63 lines
1.3 KiB
63 lines
1.3 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/pci.h>
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#include <netdev.h>
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int checkboard(void)
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{
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puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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static struct pci_controller hose;
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void pci_init_board(void)
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{
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pci_sh7780_init(&hose);
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_SH_32BIT)
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int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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/* clear ITLB */
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writel(0x00000004, 0xff000010);
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/* delete PMB for peripheral */
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writel(0, PMB_ADDR_BASE(0));
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writel(0, PMB_DATA_BASE(0));
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writel(0, PMB_ADDR_BASE(1));
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writel(0, PMB_DATA_BASE(1));
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writel(0, PMB_ADDR_BASE(2));
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writel(0, PMB_DATA_BASE(2));
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/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
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writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
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writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
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writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
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writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
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return 0;
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}
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U_BOOT_CMD(
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pmb, 1, 1, do_pmb,
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"pmb - PMB setting\n",
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"\n"
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" - PMB setting for all SDRAM mapping"
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);
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#endif
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