upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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293 lines
7.1 KiB
293 lines
7.1 KiB
/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <net.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_emi.h>
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#include <asm/arch/spr_xloader_table.h>
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#include <asm/arch/spr_defs.h>
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#define CPU 0
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#define DDR 1
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#define SRAM_REL 0xD2801000
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DECLARE_GLOBAL_DATA_PTR;
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static struct chip_data chip_data;
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int dram_init(void)
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{
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struct xloader_table *xloader_tb =
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(struct xloader_table *)XLOADER_TABLE_ADDRESS;
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struct xloader_table_1_1 *table_1_1;
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struct xloader_table_1_2 *table_1_2;
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struct chip_data *chip = &chip_data;
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1,
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PHYS_SDRAM_1_MAXSIZE);
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if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) {
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table_1_1 = &xloader_tb->table.table_1_1;
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chip->dramfreq = table_1_1->ddrfreq;
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chip->dramtype = table_1_1->ddrtype;
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} else if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) {
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table_1_2 = &xloader_tb->table.table_1_2;
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chip->dramfreq = table_1_2->ddrfreq;
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chip->dramtype = table_1_2->ddrtype;
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} else {
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chip->dramfreq = -1;
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}
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return 0;
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}
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int misc_init_r(void)
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{
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#if defined(CONFIG_CMD_NET)
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uchar mac_id[6];
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if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
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eth_setenv_enetaddr("ethaddr", mac_id);
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#endif
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setenv("verify", "n");
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#if defined(CONFIG_SPEAR_USBTTY)
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setenv("stdin", "usbtty");
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setenv("stdout", "usbtty");
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setenv("stderr", "usbtty");
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#endif
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return 0;
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}
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#ifdef CONFIG_SPEAR_EMI
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struct cust_emi_para {
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unsigned int tap;
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unsigned int tsdp;
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unsigned int tdpw;
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unsigned int tdpr;
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unsigned int tdcs;
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};
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/* EMI timing setting of m28w640hc of linux kernel */
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const struct cust_emi_para emi_timing_m28w640hc = {
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.tap = 0x10,
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.tsdp = 0x05,
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.tdpw = 0x0a,
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.tdpr = 0x0a,
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.tdcs = 0x05,
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};
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/* EMI timing setting of bootrom */
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const struct cust_emi_para emi_timing_bootrom = {
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.tap = 0xf,
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.tsdp = 0x0,
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.tdpw = 0xff,
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.tdpr = 0x111,
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.tdcs = 0x02,
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};
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void spear_emi_init(void)
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{
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const struct cust_emi_para *p = &emi_timing_m28w640hc;
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struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
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unsigned int cs;
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unsigned int val, tmp;
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val = readl(CONFIG_SPEAR_RASBASE);
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if (val & EMI_ACKMSK)
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tmp = 0x3f;
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else
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tmp = 0x0;
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writel(tmp, &emi_regs_p->ack);
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for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
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writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
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writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
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writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
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writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
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writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
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writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
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&emi_regs_p->bank_regs[cs].control);
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}
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}
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#endif
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int spear_board_init(ulong mach_type)
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{
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struct xloader_table *xloader_tb =
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(struct xloader_table *)XLOADER_TABLE_ADDRESS;
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struct xloader_table_1_2 *table_1_2;
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struct chip_data *chip = &chip_data;
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gd->bd->bi_arch_number = mach_type;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
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/* CPU is initialized to work at 333MHz in Xloader */
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chip->cpufreq = 333;
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if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) {
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table_1_2 = &xloader_tb->table.table_1_2;
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memcpy(chip->version, table_1_2->version,
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sizeof(chip->version));
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}
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#ifdef CONFIG_SPEAR_EMI
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spear_emi_init();
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#endif
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return 0;
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}
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static int i2c_read_mac(uchar *buffer)
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{
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u8 buf[2];
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i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
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/* Check if mac in i2c memory is valid */
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if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
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/* Valid mac address is saved in i2c eeprom */
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i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
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return 0;
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}
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return -1;
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}
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static int write_mac(uchar *mac)
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{
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u8 buf[2];
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buf[0] = (u8)MAGIC_BYTE0;
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buf[1] = (u8)MAGIC_BYTE1;
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i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
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buf[0] = (u8)~MAGIC_BYTE0;
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buf[1] = (u8)~MAGIC_BYTE1;
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i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
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/* check if valid MAC address is saved in I2C EEPROM or not? */
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if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
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i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
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puts("I2C EEPROM written with mac address \n");
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return 0;
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}
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puts("I2C EEPROM writing failed \n");
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return -1;
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}
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int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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void (*sram_setfreq) (unsigned int, unsigned int);
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struct chip_data *chip = &chip_data;
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unsigned char mac[6];
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unsigned int reg, frequency;
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char *s, *e;
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char i2c_mac[20];
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if ((argc > 3) || (argc < 2))
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return cmd_usage(cmdtp);
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if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
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frequency = simple_strtoul(argv[2], NULL, 0);
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if (frequency > 333) {
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printf("Frequency is limited to 333MHz\n");
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return 1;
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}
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sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
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if (!strcmp(argv[1], "cpufreq")) {
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sram_setfreq(CPU, frequency);
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printf("CPU frequency changed to %u\n", frequency);
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chip->cpufreq = frequency;
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} else {
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sram_setfreq(DDR, frequency);
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printf("DDR frequency changed to %u\n", frequency);
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chip->dramfreq = frequency;
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}
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return 0;
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} else if (!strcmp(argv[1], "ethaddr")) {
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s = argv[2];
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for (reg = 0; reg < 6; ++reg) {
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mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
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if (s)
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s = (*e) ? e + 1 : e;
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}
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write_mac(mac);
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return 0;
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} else if (!strcmp(argv[1], "print")) {
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if (chip->cpufreq == -1)
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printf("CPU Freq = Not Known\n");
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else
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printf("CPU Freq = %d MHz\n", chip->cpufreq);
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if (chip->dramfreq == -1)
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printf("DDR Freq = Not Known\n");
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else
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printf("DDR Freq = %d MHz\n", chip->dramfreq);
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if (chip->dramtype == DDRMOBILE)
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printf("DDR Type = MOBILE\n");
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else if (chip->dramtype == DDR2)
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printf("DDR Type = DDR2\n");
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else
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printf("DDR Type = Not Known\n");
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if (!i2c_read_mac(mac)) {
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sprintf(i2c_mac, "%pM", mac);
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printf("Ethaddr (from i2c mem) = %s\n", i2c_mac);
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} else {
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printf("Ethaddr (from i2c mem) = Not set\n");
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}
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printf("Xloader Rev = %s\n", chip->version);
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return 0;
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}
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return cmd_usage(cmdtp);
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}
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U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
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"configure chip",
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"chip_config cpufreq/ddrfreq frequency\n"
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"chip_config print");
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