upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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144 lines
4.1 KiB
144 lines
4.1 KiB
/*
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* (C) Copyright 2000, 2001, 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8xx.h>
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/* ------------------------------------------------------------------------- */
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const uint sdram_table[] =
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{
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/*-----------------
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UPM A contents:
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----------------- */
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/*---------------------------------------------------
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Read Single Beat Cycle. Offset 0 in the RAM array.
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---------------------------------------------------- */
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0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 ,
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0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 ,
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/*------------------------------------------------
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Read Burst Cycle. Offset 0x8 in the RAM array.
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------------------------------------------------ */
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0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
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0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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/*-------------------------------------------------------
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Write Single Beat Cycle. Offset 0x18 in the RAM array
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------------------------------------------------------- */
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0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 ,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
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/*-------------------------------------------------
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Write Burst Cycle. Offset 0x20 in the RAM array
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------------------------------------------------- */
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0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
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0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
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/*------------------------------------------------------------------------
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Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array
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------------------------------------------------------------------------ */
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0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
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/*-----------
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* Exception:
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* ----------- */
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0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff ,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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* Test ID string (SVM8...)
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*
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* Return 1 for "SC8xx" type, 0 else.
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*/
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int checkboard(void)
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{
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char buf[64];
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int i;
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int l = getenv_f("serial#", buf, sizeof(buf));
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if (l < 0 || strncmp(buf, "SVM8", 4)) {
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printf("### No HW ID - assuming SVM SC8xx\n");
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return (0);
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}
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for (i = 0; i < l; ++i) {
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if (buf[i] == ' ')
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break;
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putc(buf[i]);
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}
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putc('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size_b0 = 0;
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upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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#if defined (CONFIG_SDRAM_16M)
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memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx;
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memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
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udelay(1);
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memctl->memc_mcr = 0x80002830;
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udelay(1);
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memctl->memc_mar = 0x00000088;
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udelay(1);
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memctl->memc_mcr = 0x80002106;
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udelay(1);
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memctl->memc_or1 = 0xff000a00;
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size_b0 = 0x01000000;
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#elif defined (CONFIG_SDRAM_32M)
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memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx;
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memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
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udelay(1);
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memctl->memc_mcr = 0x80002830;
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udelay(1);
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memctl->memc_mar = 0x00000088;
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udelay(1);
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memctl->memc_mcr = 0x80002106;
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udelay(1);
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memctl->memc_or1 = 0xfe000a00;
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size_b0 = 0x02000000;
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#elif defined (CONFIG_SDRAM_64M)
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memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx;
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memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
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udelay(1);
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memctl->memc_mcr = 0x80002830;
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udelay(1);
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memctl->memc_mar = 0x00000088;
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udelay(1);
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memctl->memc_mcr = 0x80002106;
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udelay(1);
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memctl->memc_or1 = 0xfc000a00;
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size_b0 = 0x04000000;
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#else
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#error SDRAM size configuration missing.
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#endif
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memctl->memc_br1 = 0x00000081;
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udelay(200);
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return (size_b0 );
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}
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#if defined(CONFIG_CMD_DOC)
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void doc_init (void)
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{
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doc_probe (CONFIG_SYS_DOC_BASE);
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}
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#endif
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