upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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710 lines
18 KiB
710 lines
18 KiB
/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* Author: Tang Yuantian <b29983@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <command.h>
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#include <asm/byteorder.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <fis.h>
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#include <sata.h>
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#include <libata.h>
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#include <sata.h>
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#include "sata_sil.h"
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/* Convert sectorsize to wordsize */
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#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
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#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
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static struct sata_info sata_info;
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static struct pci_device_id supported[] = {
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{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131},
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{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132},
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{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124},
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{}
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};
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static void sil_sata_dump_fis(struct sata_fis_d2h *s)
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{
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printf("Status FIS dump:\n");
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printf("fis_type: %02x\n", s->fis_type);
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printf("pm_port_i: %02x\n", s->pm_port_i);
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printf("status: %02x\n", s->status);
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printf("error: %02x\n", s->error);
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printf("lba_low: %02x\n", s->lba_low);
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printf("lba_mid: %02x\n", s->lba_mid);
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printf("lba_high: %02x\n", s->lba_high);
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printf("device: %02x\n", s->device);
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printf("lba_low_exp: %02x\n", s->lba_low_exp);
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printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
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printf("lba_high_exp: %02x\n", s->lba_high_exp);
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printf("res1: %02x\n", s->res1);
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printf("sector_count: %02x\n", s->sector_count);
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printf("sector_count_exp: %02x\n", s->sector_count_exp);
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}
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static const char *sata_spd_string(unsigned int speed)
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{
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static const char * const spd_str[] = {
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"1.5 Gbps",
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"3.0 Gbps",
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"6.0 Gbps",
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};
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if ((speed - 1) > 2)
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return "<unknown>";
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return spd_str[speed - 1];
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}
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static u32 ata_wait_register(void *reg, u32 mask,
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u32 val, int timeout_msec)
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{
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u32 tmp;
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tmp = readl(reg);
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while ((tmp & mask) == val && timeout_msec > 0) {
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mdelay(1);
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timeout_msec--;
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tmp = readl(reg);
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}
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return tmp;
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}
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static void sil_config_port(void *port)
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{
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/* configure IRQ WoC */
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writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
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/* zero error counters. */
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writew(0x8000, port + PORT_DECODE_ERR_THRESH);
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writew(0x8000, port + PORT_CRC_ERR_THRESH);
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writew(0x8000, port + PORT_HSHK_ERR_THRESH);
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writew(0x0000, port + PORT_DECODE_ERR_CNT);
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writew(0x0000, port + PORT_CRC_ERR_CNT);
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writew(0x0000, port + PORT_HSHK_ERR_CNT);
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/* always use 64bit activation */
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writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
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/* clear port multiplier enable and resume bits */
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writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
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}
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static int sil_init_port(void *port)
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{
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u32 tmp;
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writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
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ata_wait_register(port + PORT_CTRL_STAT,
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PORT_CS_INIT, PORT_CS_INIT, 100);
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tmp = ata_wait_register(port + PORT_CTRL_STAT,
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PORT_CS_RDY, 0, 100);
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if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
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return 1;
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return 0;
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}
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static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
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{
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struct sil_sata *sata = sata_dev_desc[dev].priv;
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void *port = sata->port;
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struct sil_prb *prb;
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int i;
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u32 *src, *dst;
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prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
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src = (u32 *)&prb->fis;
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dst = (u32 *)fis;
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for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
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*dst++ = readl(src++);
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}
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static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
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{
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struct sil_sata *sata = sata_dev_desc[dev].priv;
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void *port = sata->port;
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u64 paddr = virt_to_bus(sata->devno, pcmd);
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u32 irq_mask, irq_stat;
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int rc;
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writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
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/* better to add momery barrior here */
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writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
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writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
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irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
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irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
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0, 10000);
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/* clear IRQs */
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writel(irq_mask, port + PORT_IRQ_STAT);
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irq_stat >>= PORT_IRQ_RAW_SHIFT;
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if (irq_stat & PORT_IRQ_COMPLETE)
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rc = 0;
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else {
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/* force port into known state */
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sil_init_port(port);
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if (irq_stat & PORT_IRQ_ERROR)
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rc = 1; /* error */
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else
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rc = 2; /* busy */
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}
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return rc;
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}
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static int sil_cmd_set_feature(int dev)
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{
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struct sil_sata *sata = sata_dev_desc[dev].priv;
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struct sil_cmd_block cmdb, *pcmd = &cmdb;
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struct sata_fis_d2h fis;
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u8 udma_cap;
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int ret;
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memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
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pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
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pcmd->prb.fis.pm_port_c = (1 << 7);
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pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
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pcmd->prb.fis.features = SETFEATURES_XFER;
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/* First check the device capablity */
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udma_cap = (u8)(sata->udma & 0xff);
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debug("udma_cap %02x\n", udma_cap);
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if (udma_cap == ATA_UDMA6)
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pcmd->prb.fis.sector_count = XFER_UDMA_6;
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if (udma_cap == ATA_UDMA5)
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pcmd->prb.fis.sector_count = XFER_UDMA_5;
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if (udma_cap == ATA_UDMA4)
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pcmd->prb.fis.sector_count = XFER_UDMA_4;
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if (udma_cap == ATA_UDMA3)
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pcmd->prb.fis.sector_count = XFER_UDMA_3;
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ret = sil_exec_cmd(dev, pcmd, 0);
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if (ret) {
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sil_read_fis(dev, 0, &fis);
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printf("Err: exe cmd(0x%x).\n",
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readl(sata->port + PORT_SERROR));
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sil_sata_dump_fis(&fis);
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return 1;
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}
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return 0;
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}
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static int sil_cmd_identify_device(int dev, u16 *id)
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{
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struct sil_sata *sata = sata_dev_desc[dev].priv;
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struct sil_cmd_block cmdb, *pcmd = &cmdb;
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struct sata_fis_d2h fis;
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int ret;
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memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
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pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
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pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
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pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
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pcmd->prb.fis.pm_port_c = (1 << 7);
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pcmd->prb.fis.command = ATA_CMD_ID_ATA;
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pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
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pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
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pcmd->sge.flags = cpu_to_le32(SGE_TRM);
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ret = sil_exec_cmd(dev, pcmd, 0);
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if (ret) {
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sil_read_fis(dev, 0, &fis);
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printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
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sil_sata_dump_fis(&fis);
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return 1;
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}
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ata_swap_buf_le16(id, ATA_ID_WORDS);
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return 0;
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}
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static int sil_cmd_soft_reset(int dev)
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{
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struct sil_cmd_block cmdb, *pcmd = &cmdb;
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struct sil_sata *sata = sata_dev_desc[dev].priv;
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struct sata_fis_d2h fis;
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void *port = sata->port;
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int ret;
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/* put the port into known state */
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if (sil_init_port(port)) {
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printf("SRST: port %d not ready\n", dev);
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return 1;
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}
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memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
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pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
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pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
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pcmd->prb.fis.pm_port_c = 0xf;
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ret = sil_exec_cmd(dev, &cmdb, 0);
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if (ret) {
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sil_read_fis(dev, 0, &fis);
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printf("SRST cmd error.\n");
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sil_sata_dump_fis(&fis);
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return 1;
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}
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return 0;
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}
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static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
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u8 *buffer, int is_write)
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{
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struct sil_sata *sata = sata_dev_desc[dev].priv;
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struct sil_cmd_block cmdb, *pcmd = &cmdb;
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struct sata_fis_d2h fis;
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u64 block;
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int ret;
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block = (u64)start;
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memset(pcmd, 0, sizeof(struct sil_cmd_block));
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pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
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pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
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pcmd->prb.fis.pm_port_c = (1 << 7);
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if (is_write) {
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pcmd->prb.fis.command = ATA_CMD_WRITE;
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pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
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} else {
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pcmd->prb.fis.command = ATA_CMD_READ;
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pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
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}
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pcmd->prb.fis.device = ATA_LBA;
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pcmd->prb.fis.device |= (block >> 24) & 0xf;
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pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
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pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
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pcmd->prb.fis.lba_low = block & 0xff;
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pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
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pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
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pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
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pcmd->sge.flags = cpu_to_le32(SGE_TRM);
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ret = sil_exec_cmd(dev, pcmd, 0);
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if (ret) {
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sil_read_fis(dev, 0, &fis);
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printf("Err: rw cmd(0x%08x).\n",
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readl(sata->port + PORT_SERROR));
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sil_sata_dump_fis(&fis);
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return 1;
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}
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return blkcnt;
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}
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static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
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u8 *buffer, int is_write)
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{
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struct sil_sata *sata = sata_dev_desc[dev].priv;
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struct sil_cmd_block cmdb, *pcmd = &cmdb;
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struct sata_fis_d2h fis;
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u64 block;
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int ret;
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block = (u64)start;
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memset(pcmd, 0, sizeof(struct sil_cmd_block));
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pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
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pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
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pcmd->prb.fis.pm_port_c = (1 << 7);
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if (is_write) {
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pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
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pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
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} else {
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pcmd->prb.fis.command = ATA_CMD_READ_EXT;
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pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
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}
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pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
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pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
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pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
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pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
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pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
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pcmd->prb.fis.lba_low = block & 0xff;
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pcmd->prb.fis.device = ATA_LBA;
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pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
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pcmd->prb.fis.sector_count = blkcnt & 0xff;
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pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
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pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
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pcmd->sge.flags = cpu_to_le32(SGE_TRM);
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ret = sil_exec_cmd(dev, pcmd, 0);
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if (ret) {
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sil_read_fis(dev, 0, &fis);
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printf("Err: rw ext cmd(0x%08x).\n",
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readl(sata->port + PORT_SERROR));
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sil_sata_dump_fis(&fis);
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return 1;
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}
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return blkcnt;
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}
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static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
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const void *buffer, int is_write)
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{
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ulong start, blks, max_blks;
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u8 *addr;
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start = blknr;
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blks = blkcnt;
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addr = (u8 *)buffer;
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max_blks = ATA_MAX_SECTORS;
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do {
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if (blks > max_blks) {
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sil_sata_rw_cmd(dev, start, max_blks, addr, is_write);
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start += max_blks;
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blks -= max_blks;
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addr += ATA_SECT_SIZE * max_blks;
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} else {
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sil_sata_rw_cmd(dev, start, blks, addr, is_write);
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start += blks;
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blks = 0;
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addr += ATA_SECT_SIZE * blks;
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}
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} while (blks != 0);
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return blkcnt;
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}
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static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
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const void *buffer, int is_write)
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{
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ulong start, blks, max_blks;
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u8 *addr;
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start = blknr;
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blks = blkcnt;
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addr = (u8 *)buffer;
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max_blks = ATA_MAX_SECTORS_LBA48;
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do {
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if (blks > max_blks) {
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sil_sata_rw_cmd_ext(dev, start, max_blks,
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addr, is_write);
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start += max_blks;
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blks -= max_blks;
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addr += ATA_SECT_SIZE * max_blks;
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} else {
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sil_sata_rw_cmd_ext(dev, start, blks,
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addr, is_write);
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start += blks;
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blks = 0;
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addr += ATA_SECT_SIZE * blks;
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}
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} while (blks != 0);
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return blkcnt;
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}
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static void sil_sata_cmd_flush_cache(int dev)
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{
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struct sil_cmd_block cmdb, *pcmd = &cmdb;
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memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
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pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
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pcmd->prb.fis.pm_port_c = (1 << 7);
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pcmd->prb.fis.command = ATA_CMD_FLUSH;
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sil_exec_cmd(dev, pcmd, 0);
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}
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static void sil_sata_cmd_flush_cache_ext(int dev)
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{
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struct sil_cmd_block cmdb, *pcmd = &cmdb;
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memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
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pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
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pcmd->prb.fis.pm_port_c = (1 << 7);
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pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
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sil_exec_cmd(dev, pcmd, 0);
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}
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static void sil_sata_init_wcache(int dev, u16 *id)
|
|
{
|
|
struct sil_sata *sata = sata_dev_desc[dev].priv;
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|
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|
if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
|
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sata->wcache = 1;
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|
if (ata_id_has_flush(id))
|
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sata->flush = 1;
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if (ata_id_has_flush_ext(id))
|
|
sata->flush_ext = 1;
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|
}
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|
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static int sil_sata_get_wcache(int dev)
|
|
{
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|
struct sil_sata *sata = sata_dev_desc[dev].priv;
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|
|
|
return sata->wcache;
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}
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|
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static int sil_sata_get_flush(int dev)
|
|
{
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|
struct sil_sata *sata = sata_dev_desc[dev].priv;
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|
|
|
return sata->flush;
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}
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|
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static int sil_sata_get_flush_ext(int dev)
|
|
{
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|
struct sil_sata *sata = sata_dev_desc[dev].priv;
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|
|
|
return sata->flush_ext;
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|
}
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|
|
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/*
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* SATA interface between low level driver and command layer
|
|
*/
|
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ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
|
|
{
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|
struct sil_sata *sata = sata_dev_desc[dev].priv;
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ulong rc;
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|
|
|
if (sata->lba48)
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rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
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else
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rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
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|
|
|
return rc;
|
|
}
|
|
|
|
/*
|
|
* SATA interface between low level driver and command layer
|
|
*/
|
|
ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
|
|
{
|
|
struct sil_sata *sata = sata_dev_desc[dev].priv;
|
|
ulong rc;
|
|
|
|
if (sata->lba48) {
|
|
rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
|
|
if (sil_sata_get_wcache(dev) && sil_sata_get_flush_ext(dev))
|
|
sil_sata_cmd_flush_cache_ext(dev);
|
|
} else {
|
|
rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
|
|
if (sil_sata_get_wcache(dev) && sil_sata_get_flush(dev))
|
|
sil_sata_cmd_flush_cache(dev);
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
/*
|
|
* SATA interface between low level driver and command layer
|
|
*/
|
|
int init_sata(int dev)
|
|
{
|
|
static int init_done, idx;
|
|
pci_dev_t devno;
|
|
u16 word;
|
|
|
|
if (init_done == 1 && dev < sata_info.maxport)
|
|
return 1;
|
|
|
|
init_done = 1;
|
|
|
|
/* Find PCI device(s) */
|
|
devno = pci_find_devices(supported, idx++);
|
|
if (devno == -1)
|
|
return 1;
|
|
|
|
pci_read_config_word(devno, PCI_DEVICE_ID, &word);
|
|
|
|
/* get the port count */
|
|
word &= 0xf;
|
|
|
|
sata_info.portbase = sata_info.maxport;
|
|
sata_info.maxport = sata_info.portbase + word;
|
|
sata_info.devno = devno;
|
|
|
|
/* Read out all BARs */
|
|
sata_info.iobase[0] = (ulong)pci_map_bar(devno,
|
|
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
|
|
sata_info.iobase[1] = (ulong)pci_map_bar(devno,
|
|
PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
|
|
sata_info.iobase[2] = (ulong)pci_map_bar(devno,
|
|
PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
|
|
|
|
/* mask out the unused bits */
|
|
sata_info.iobase[0] &= 0xffffff80;
|
|
sata_info.iobase[1] &= 0xfffffc00;
|
|
sata_info.iobase[2] &= 0xffffff80;
|
|
|
|
/* Enable Bus Mastering and memory region */
|
|
pci_write_config_word(devno, PCI_COMMAND,
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
|
|
/* Check if mem accesses and Bus Mastering are enabled. */
|
|
pci_read_config_word(devno, PCI_COMMAND, &word);
|
|
if (!(word & PCI_COMMAND_MEMORY) ||
|
|
(!(word & PCI_COMMAND_MASTER))) {
|
|
printf("Error: Can not enable MEM access or Bus Mastering.\n");
|
|
debug("PCI command: %04x\n", word);
|
|
return 1;
|
|
}
|
|
|
|
/* GPIO off */
|
|
writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
|
|
/* clear global reset & mask interrupts during initialization */
|
|
writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* SATA interface between low level driver and command layer
|
|
*/
|
|
int scan_sata(int dev)
|
|
{
|
|
unsigned char serial[ATA_ID_SERNO_LEN + 1];
|
|
unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
|
|
unsigned char product[ATA_ID_PROD_LEN + 1];
|
|
struct sil_sata *sata;
|
|
void *port;
|
|
int cnt;
|
|
u16 *id;
|
|
u32 tmp;
|
|
|
|
if (dev >= sata_info.maxport) {
|
|
printf("SATA#%d is not present\n", dev);
|
|
return 1;
|
|
}
|
|
|
|
printf("SATA#%d\n", dev);
|
|
port = (void *)sata_info.iobase[1] +
|
|
PORT_REGS_SIZE * (dev - sata_info.portbase);
|
|
|
|
/* Initial PHY setting */
|
|
writel(0x20c, port + PORT_PHY_CFG);
|
|
|
|
/* clear port RST */
|
|
tmp = readl(port + PORT_CTRL_STAT);
|
|
if (tmp & PORT_CS_PORT_RST) {
|
|
writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
|
|
tmp = ata_wait_register(port + PORT_CTRL_STAT,
|
|
PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
|
|
if (tmp & PORT_CS_PORT_RST)
|
|
printf("Err: Failed to clear port RST\n");
|
|
}
|
|
|
|
/* Check if device is present */
|
|
for (cnt = 0; cnt < 100; cnt++) {
|
|
tmp = readl(port + PORT_SSTATUS);
|
|
if ((tmp & 0xF) == 0x3)
|
|
break;
|
|
mdelay(1);
|
|
}
|
|
|
|
tmp = readl(port + PORT_SSTATUS);
|
|
if ((tmp & 0xf) != 0x3) {
|
|
printf(" (No RDY)\n");
|
|
return 1;
|
|
}
|
|
|
|
/* Wait for port ready */
|
|
tmp = ata_wait_register(port + PORT_CTRL_STAT,
|
|
PORT_CS_RDY, PORT_CS_RDY, 100);
|
|
if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
|
|
printf("%d port not ready.\n", dev);
|
|
return 1;
|
|
}
|
|
|
|
/* configure port */
|
|
sil_config_port(port);
|
|
|
|
/* Reset port */
|
|
writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
|
|
readl(port + PORT_CTRL_STAT);
|
|
tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
|
|
PORT_CS_DEV_RST, 100);
|
|
if (tmp & PORT_CS_DEV_RST) {
|
|
printf("%d port reset failed.\n", dev);
|
|
return 1;
|
|
}
|
|
|
|
sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
|
|
if (!sata) {
|
|
printf("%d no memory.\n", dev);
|
|
return 1;
|
|
}
|
|
memset((void *)sata, 0, sizeof(struct sil_sata));
|
|
|
|
/* turn on port interrupt */
|
|
tmp = readl((void *)(sata_info.iobase[0] + HOST_CTRL));
|
|
tmp |= (1 << (dev - sata_info.portbase));
|
|
writel(tmp, (void *)(sata_info.iobase[0] + HOST_CTRL));
|
|
|
|
/* Save the private struct to block device struct */
|
|
sata_dev_desc[dev].priv = (void *)sata;
|
|
sata->port = port;
|
|
sata->devno = sata_info.devno;
|
|
sprintf(sata->name, "SATA#%d", dev);
|
|
sil_cmd_soft_reset(dev);
|
|
tmp = readl(port + PORT_SSTATUS);
|
|
tmp = (tmp >> 4) & 0xf;
|
|
printf(" (%s)\n", sata_spd_string(tmp));
|
|
|
|
id = (u16 *)malloc(ATA_ID_WORDS * 2);
|
|
if (!id) {
|
|
printf("Id malloc failed\n");
|
|
free((void *)sata);
|
|
return 1;
|
|
}
|
|
sil_cmd_identify_device(dev, id);
|
|
|
|
#ifdef CONFIG_LBA48
|
|
/* Check if support LBA48 */
|
|
if (ata_id_has_lba48(id)) {
|
|
sata_dev_desc[dev].lba48 = 1;
|
|
sata->lba48 = 1;
|
|
debug("Device supports LBA48\n");
|
|
} else
|
|
debug("Device supports LBA28\n");
|
|
#endif
|
|
|
|
/* Serial number */
|
|
ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
|
|
memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
|
|
|
|
/* Firmware version */
|
|
ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
|
|
memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
|
|
|
|
/* Product model */
|
|
ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
|
|
memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
|
|
|
|
/* Totoal sectors */
|
|
sata_dev_desc[dev].lba = ata_id_n_sectors(id);
|
|
|
|
sil_sata_init_wcache(dev, id);
|
|
sil_cmd_set_feature(dev);
|
|
|
|
#ifdef DEBUG
|
|
sil_cmd_identify_device(dev, id);
|
|
ata_dump_id(id);
|
|
#endif
|
|
free((void *)id);
|
|
|
|
return 0;
|
|
}
|
|
|