upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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427 lines
11 KiB
427 lines
11 KiB
/*
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* Freescale i.MX28 SSP MMC driver
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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* Terry Lv
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*
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* Copyright 2007, Freescale Semiconductor, Inc
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* Andy Fleming
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*
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* Based vaguely on the pxa mmc code:
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* (C) Copyright 2003
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/dma.h>
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#include <bouncebuf.h>
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struct mxsmmc_priv {
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int id;
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struct mxs_ssp_regs *regs;
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uint32_t buswidth;
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int (*mmc_is_wp)(int);
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int (*mmc_cd)(int);
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struct mxs_dma_desc *desc;
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};
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#define MXSMMC_MAX_TIMEOUT 10000
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#define MXSMMC_SMALL_TRANSFER 512
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static int mxsmmc_cd(struct mxsmmc_priv *priv)
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{
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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if (priv->mmc_cd)
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return priv->mmc_cd(priv->id);
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return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
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}
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static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
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{
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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uint32_t *data_ptr;
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int timeout = MXSMMC_MAX_TIMEOUT;
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uint32_t reg;
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uint32_t data_count = data->blocksize * data->blocks;
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if (data->flags & MMC_DATA_READ) {
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data_ptr = (uint32_t *)data->dest;
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while (data_count && --timeout) {
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reg = readl(&ssp_regs->hw_ssp_status);
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if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
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*data_ptr++ = readl(&ssp_regs->hw_ssp_data);
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data_count -= 4;
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timeout = MXSMMC_MAX_TIMEOUT;
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} else
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udelay(1000);
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}
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} else {
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data_ptr = (uint32_t *)data->src;
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timeout *= 100;
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while (data_count && --timeout) {
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reg = readl(&ssp_regs->hw_ssp_status);
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if (!(reg & SSP_STATUS_FIFO_FULL)) {
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writel(*data_ptr++, &ssp_regs->hw_ssp_data);
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data_count -= 4;
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timeout = MXSMMC_MAX_TIMEOUT;
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} else
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udelay(1000);
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}
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}
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return timeout ? 0 : COMM_ERR;
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}
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static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
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{
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uint32_t data_count = data->blocksize * data->blocks;
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int dmach;
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struct mxs_dma_desc *desc = priv->desc;
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void *addr;
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unsigned int flags;
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struct bounce_buffer bbstate;
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memset(desc, 0, sizeof(struct mxs_dma_desc));
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desc->address = (dma_addr_t)desc;
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if (data->flags & MMC_DATA_READ) {
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priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
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addr = data->dest;
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flags = GEN_BB_WRITE;
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} else {
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priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
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addr = (void *)data->src;
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flags = GEN_BB_READ;
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}
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bounce_buffer_start(&bbstate, addr, data_count, flags);
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priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
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priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
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(data_count << MXS_DMA_DESC_BYTES_OFFSET);
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dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
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mxs_dma_desc_append(dmach, priv->desc);
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if (mxs_dma_go(dmach)) {
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bounce_buffer_stop(&bbstate);
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return COMM_ERR;
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}
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bounce_buffer_stop(&bbstate);
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return 0;
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}
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/*
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* Sends a command out on the bus. Takes the mmc pointer,
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* a command pointer, and an optional data pointer.
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*/
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static int
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mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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{
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struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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uint32_t reg;
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int timeout;
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uint32_t ctrl0;
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int ret;
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debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
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/* Check bus busy */
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timeout = MXSMMC_MAX_TIMEOUT;
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while (--timeout) {
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udelay(1000);
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reg = readl(&ssp_regs->hw_ssp_status);
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if (!(reg &
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(SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
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SSP_STATUS_CMD_BUSY))) {
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break;
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}
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}
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if (!timeout) {
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printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
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return TIMEOUT;
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}
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/* See if card is present */
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if (!mxsmmc_cd(priv)) {
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printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
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return NO_CARD_ERR;
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}
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/* Start building CTRL0 contents */
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ctrl0 = priv->buswidth;
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/* Set up command */
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if (!(cmd->resp_type & MMC_RSP_CRC))
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ctrl0 |= SSP_CTRL0_IGNORE_CRC;
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if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
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ctrl0 |= SSP_CTRL0_GET_RESP;
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if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
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ctrl0 |= SSP_CTRL0_LONG_RESP;
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if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
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writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
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else
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writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
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/* Command index */
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reg = readl(&ssp_regs->hw_ssp_cmd0);
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reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
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reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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reg |= SSP_CMD0_APPEND_8CYC;
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writel(reg, &ssp_regs->hw_ssp_cmd0);
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/* Command argument */
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writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
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/* Set up data */
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if (data) {
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/* READ or WRITE */
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if (data->flags & MMC_DATA_READ) {
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ctrl0 |= SSP_CTRL0_READ;
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} else if (priv->mmc_is_wp &&
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priv->mmc_is_wp(mmc->block_dev.dev)) {
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printf("MMC%d: Can not write a locked card!\n",
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mmc->block_dev.dev);
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return UNUSABLE_ERR;
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}
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ctrl0 |= SSP_CTRL0_DATA_XFER;
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reg = data->blocksize * data->blocks;
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#if defined(CONFIG_MX23)
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ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
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clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
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SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
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((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
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((ffs(data->blocksize) - 1) <<
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SSP_CMD0_BLOCK_SIZE_OFFSET));
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#elif defined(CONFIG_MX28)
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writel(reg, &ssp_regs->hw_ssp_xfer_size);
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reg = ((data->blocks - 1) <<
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SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
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((ffs(data->blocksize) - 1) <<
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SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
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writel(reg, &ssp_regs->hw_ssp_block_size);
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#endif
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}
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/* Kick off the command */
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ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
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writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
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/* Wait for the command to complete */
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timeout = MXSMMC_MAX_TIMEOUT;
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while (--timeout) {
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udelay(1000);
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reg = readl(&ssp_regs->hw_ssp_status);
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if (!(reg & SSP_STATUS_CMD_BUSY))
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break;
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}
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if (!timeout) {
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printf("MMC%d: Command %d busy\n",
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mmc->block_dev.dev, cmd->cmdidx);
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return TIMEOUT;
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}
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/* Check command timeout */
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if (reg & SSP_STATUS_RESP_TIMEOUT) {
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printf("MMC%d: Command %d timeout (status 0x%08x)\n",
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mmc->block_dev.dev, cmd->cmdidx, reg);
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return TIMEOUT;
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}
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/* Check command errors */
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if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
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printf("MMC%d: Command %d error (status 0x%08x)!\n",
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mmc->block_dev.dev, cmd->cmdidx, reg);
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return COMM_ERR;
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}
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/* Copy response to response buffer */
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
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cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
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cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
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cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
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} else
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cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
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/* Return if no data to process */
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if (!data)
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return 0;
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if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
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ret = mxsmmc_send_cmd_pio(priv, data);
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if (ret) {
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printf("MMC%d: Data timeout with command %d "
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"(status 0x%08x)!\n",
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mmc->block_dev.dev, cmd->cmdidx, reg);
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return ret;
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}
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} else {
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ret = mxsmmc_send_cmd_dma(priv, data);
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if (ret) {
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printf("MMC%d: DMA transfer failed\n",
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mmc->block_dev.dev);
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return ret;
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}
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}
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/* Check data errors */
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reg = readl(&ssp_regs->hw_ssp_status);
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if (reg &
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(SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
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SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
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printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
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mmc->block_dev.dev, cmd->cmdidx, reg);
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return COMM_ERR;
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}
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return 0;
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}
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static void mxsmmc_set_ios(struct mmc *mmc)
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{
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struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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/* Set the clock speed */
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if (mmc->clock)
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mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
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switch (mmc->bus_width) {
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case 1:
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priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
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break;
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case 4:
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priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
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break;
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case 8:
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priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
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break;
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}
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/* Set the bus width */
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clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
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SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
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debug("MMC%d: Set %d bits bus width\n",
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mmc->block_dev.dev, mmc->bus_width);
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}
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static int mxsmmc_init(struct mmc *mmc)
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{
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struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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/* Reset SSP */
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mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
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/* Reconfigure the SSP block for MMC operation */
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writel(SSP_CTRL1_SSP_MODE_SD_MMC |
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SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
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SSP_CTRL1_DMA_ENABLE |
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SSP_CTRL1_POLARITY |
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SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
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SSP_CTRL1_DATA_CRC_IRQ_EN |
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SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
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SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
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SSP_CTRL1_RESP_ERR_IRQ_EN,
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&ssp_regs->hw_ssp_ctrl1_set);
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/* Set initial bit clock 400 KHz */
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mxs_set_ssp_busclock(priv->id, 400);
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/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
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writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
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udelay(200);
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writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
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return 0;
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}
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int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
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{
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struct mmc *mmc = NULL;
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struct mxsmmc_priv *priv = NULL;
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int ret;
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const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
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if (!mxs_ssp_bus_id_valid(id))
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return -ENODEV;
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mmc = malloc(sizeof(struct mmc));
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if (!mmc)
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return -ENOMEM;
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priv = malloc(sizeof(struct mxsmmc_priv));
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if (!priv) {
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free(mmc);
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return -ENOMEM;
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}
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priv->desc = mxs_dma_desc_alloc();
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if (!priv->desc) {
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free(priv);
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free(mmc);
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return -ENOMEM;
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}
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ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
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if (ret)
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return ret;
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priv->mmc_is_wp = wp;
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priv->mmc_cd = cd;
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priv->id = id;
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priv->regs = mxs_ssp_regs_by_bus(id);
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sprintf(mmc->name, "MXS MMC");
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mmc->send_cmd = mxsmmc_send_cmd;
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mmc->set_ios = mxsmmc_set_ios;
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mmc->init = mxsmmc_init;
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mmc->getcd = NULL;
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mmc->getwp = NULL;
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mmc->priv = priv;
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mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
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mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
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MMC_MODE_HS_52MHz | MMC_MODE_HS;
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/*
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* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
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* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
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* CLOCK_DIVIDE has to be an even value from 2 to 254, and
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* CLOCK_RATE could be any integer from 0 to 255.
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*/
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mmc->f_min = 400000;
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mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
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mmc->b_max = 0x20;
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mmc_register(mmc);
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return 0;
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}
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