upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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93 lines
3.2 KiB
93 lines
3.2 KiB
/*
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/macro.h>
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.globl lowlevel_init
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lowlevel_init:
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/* Also setup the Peripheral Port Remap register inside the core */
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ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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write32 IPU_CONF, IPU_CONF_DI_EN
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write32 CCM_CCMR, CCM_CCMR_SETUP
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wait_timer 0x40000
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write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
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write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
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/* Set up clock to 532MHz */
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write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
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write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
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write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
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/* Set up MX31 DDR pins */
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write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
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write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
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write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
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write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
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write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
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write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
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write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
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write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
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write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
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write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
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write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
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write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
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write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
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write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
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write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
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write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
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write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
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write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
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write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
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write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
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write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
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write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
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write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
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write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
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write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
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write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
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write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
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/* Set up MX31 DDR Memory Controller */
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write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
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write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
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/* Perform DDR init sequence */
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write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
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write32 CSD0_BASE | 0x0f00, 0x12344321
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write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
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write32 CSD0_BASE, 0x12344321
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write32 CSD0_BASE, 0x12344321
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write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
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write8 CSD0_BASE | 0x00000033, 0xda
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write8 CSD0_BASE | 0x01000000, 0xff
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write32 WEIM_ESDCTL0, ESDCTL_RW
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write32 CSD0_BASE, 0xDEADBEEF
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write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
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mov pc, lr
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