upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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196 lines
5.7 KiB
196 lines
5.7 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* (C) Copyright 2008
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* (C) Copyright 2010-2013
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* Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
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* Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#if defined(CONFIG_KMSUPX5)
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#define CONFIG_KM_BOARD_NAME "kmsupx5"
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#define CONFIG_HOSTNAME "kmsupx5"
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#elif defined(CONFIG_TUGE1)
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#define CONFIG_KM_BOARD_NAME "tuge1"
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#define CONFIG_HOSTNAME "tuge1"
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#elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */
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#define CONFIG_KM_BOARD_NAME "tuxx1"
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#define CONFIG_HOSTNAME "tuxx1"
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#elif defined(CONFIG_KMOPTI2)
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#define CONFIG_KM_BOARD_NAME "kmopti2"
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#define CONFIG_HOSTNAME "kmopti2"
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#elif defined(CONFIG_KMTEPR2)
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#define CONFIG_KM_BOARD_NAME "kmtepr2"
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#define CONFIG_HOSTNAME "kmtepr2"
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#else
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#error ("Board not supported")
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#endif
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/* include common defines/options for all 8321 Keymile boards */
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#include "km/km8321-common.h"
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#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2)
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#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
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#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
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#endif
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/*
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* Init Local Bus Memory Controller:
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* Device on board
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* Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2
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* -----------------------------------------------------------------------------
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* 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE
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* 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit)
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*
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* Device on board (continued)
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* Bank Bus Machine PortSz Size KMTEPR2
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* -----------------------------------------------------------------------------
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* 2 Local GPCM 8 bit 256MB NVRAM
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* 3 Local GPCM 8 bit 256MB TEP2 (16 bit)
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*/
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#if defined(CONFIG_KMTEPRO2)
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/*
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* Configuration for C2 (NVRAM) on the local bus
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*/
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
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#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
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BR_PS_8 | \
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BR_MS_GPCM | \
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BR_V)
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#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV2 | \
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OR_GPCM_XACS | \
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OR_GPCM_SCY_2 | \
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OR_GPCM_TRLX_SET | \
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OR_GPCM_EHTR_SET | \
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OR_GPCM_EAD)
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#else
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/*
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* Configuration for C2 on the local bus
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*/
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
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/* Window size: 256 MB */
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#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
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BR_PS_8 | \
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BR_MS_GPCM | \
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BR_V)
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#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV4 | \
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OR_GPCM_SCY_2 | \
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OR_GPCM_TRLX_SET | \
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OR_GPCM_EHTR_CLEAR | \
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OR_GPCM_EAD)
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#endif
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#if defined(CONFIG_TUXX1)
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/*
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* Configuration for C3 on the local bus
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*/
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/* Access window base at PINC3 base */
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
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/* Window size: 256 MB */
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#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
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BR_PS_8 | \
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BR_MS_GPCM | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_2 | \
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OR_GPCM_TRLX_SET | \
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OR_GPCM_EHTR_CLEAR)
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#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
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0x0000c000 | \
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MxMR_WLFx_2X)
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#endif
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#if defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2)
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/*
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* Configuration for C3 on the local bus
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*/
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
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#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
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BR_PS_16 | \
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BR_MS_GPCM | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
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OR_GPCM_SCY_4 | \
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OR_GPCM_TRLX_CLEAR | \
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OR_GPCM_EHTR_CLEAR)
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#endif
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/*
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* MMU Setup
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*/
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/* APP1: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \
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BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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/* 512M should also include APP2... */
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \
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BATU_BL_256M | \
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BATU_VS | \
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BATU_VP)
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#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \
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BATL_PP_RW | \
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BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5)
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#define CONFIG_SYS_IBAT6L (0)
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#define CONFIG_SYS_IBAT6U (0)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#else
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/* APP2: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \
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BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \
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BATU_BL_256M | \
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BATU_VS | \
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BATU_VP)
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#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \
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BATL_PP_RW | \
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BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#endif
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#define CONFIG_SYS_IBAT7L (0)
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#define CONFIG_SYS_IBAT7U (0)
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#endif /* __CONFIG_H */
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