upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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363 lines
8.7 KiB
363 lines
8.7 KiB
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/types.h>
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/utils.h>
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#define ARMV7_DCACHE_INVAL_ALL 1
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#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
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#define ARMV7_DCACHE_INVAL_RANGE 3
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#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
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#ifndef CONFIG_SYS_DCACHE_OFF
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/*
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* Write the level and type you want to Cache Size Selection Register(CSSELR)
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* to get size details from Current Cache Size ID Register(CCSIDR)
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*/
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static void set_csselr(u32 level, u32 type)
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{
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u32 csselr = level << 1 | type;
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/* Write to Cache Size Selection Register(CSSELR) */
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asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
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}
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static u32 get_ccsidr(void)
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{
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u32 ccsidr;
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/* Read current CP15 Cache Size ID Register */
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asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
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return ccsidr;
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}
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static u32 get_clidr(void)
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{
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u32 clidr;
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/* Read current CP15 Cache Level ID Register */
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asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
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return clidr;
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}
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static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
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u32 num_ways, u32 way_shift,
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u32 log2_line_len)
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{
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int way, set;
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u32 setway;
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/*
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* For optimal assembly code:
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* a. count down
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* b. have bigger loop inside
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*/
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for (way = num_ways - 1; way >= 0 ; way--) {
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for (set = num_sets - 1; set >= 0; set--) {
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setway = (level << 1) | (set << log2_line_len) |
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(way << way_shift);
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/* Invalidate data/unified cache line by set/way */
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asm volatile (" mcr p15, 0, %0, c7, c6, 2"
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: : "r" (setway));
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}
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}
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/* DSB to make sure the operation is complete */
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DSB;
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}
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static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
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u32 num_ways, u32 way_shift,
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u32 log2_line_len)
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{
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int way, set;
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u32 setway;
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/*
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* For optimal assembly code:
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* a. count down
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* b. have bigger loop inside
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*/
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for (way = num_ways - 1; way >= 0 ; way--) {
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for (set = num_sets - 1; set >= 0; set--) {
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setway = (level << 1) | (set << log2_line_len) |
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(way << way_shift);
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/*
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* Clean & Invalidate data/unified
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* cache line by set/way
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*/
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asm volatile (" mcr p15, 0, %0, c7, c14, 2"
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: : "r" (setway));
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}
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}
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/* DSB to make sure the operation is complete */
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DSB;
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}
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static void v7_maint_dcache_level_setway(u32 level, u32 operation)
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{
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u32 ccsidr;
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u32 num_sets, num_ways, log2_line_len, log2_num_ways;
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u32 way_shift;
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set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
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ccsidr = get_ccsidr();
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log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
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CCSIDR_LINE_SIZE_OFFSET) + 2;
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/* Converting from words to bytes */
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log2_line_len += 2;
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num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
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CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
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num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
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CCSIDR_NUM_SETS_OFFSET) + 1;
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/*
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* According to ARMv7 ARM number of sets and number of ways need
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* not be a power of 2
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*/
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log2_num_ways = log_2_n_round_up(num_ways);
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way_shift = (32 - log2_num_ways);
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if (operation == ARMV7_DCACHE_INVAL_ALL) {
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v7_inval_dcache_level_setway(level, num_sets, num_ways,
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way_shift, log2_line_len);
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} else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
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v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
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way_shift, log2_line_len);
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}
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}
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static void v7_maint_dcache_all(u32 operation)
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{
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u32 level, cache_type, level_start_bit = 0;
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u32 clidr = get_clidr();
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for (level = 0; level < 7; level++) {
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cache_type = (clidr >> level_start_bit) & 0x7;
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if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
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(cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
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(cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
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v7_maint_dcache_level_setway(level, operation);
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level_start_bit += 3;
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}
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}
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static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
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{
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u32 mva;
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/* Align start to cache line boundary */
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start &= ~(line_len - 1);
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for (mva = start; mva < stop; mva = mva + line_len) {
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/* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
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asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
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}
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}
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static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
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{
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u32 mva;
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/*
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* If start address is not aligned to cache-line do not
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* invalidate the first cache-line
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*/
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if (start & (line_len - 1)) {
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printf("ERROR: %s - start address is not aligned - 0x%08x\n",
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__func__, start);
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/* move to next cache line */
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start = (start + line_len - 1) & ~(line_len - 1);
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}
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/*
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* If stop address is not aligned to cache-line do not
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* invalidate the last cache-line
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*/
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if (stop & (line_len - 1)) {
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printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
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__func__, stop);
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/* align to the beginning of this cache line */
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stop &= ~(line_len - 1);
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}
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for (mva = start; mva < stop; mva = mva + line_len) {
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/* DCIMVAC - Invalidate data cache by MVA to PoC */
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asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
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}
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}
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static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
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{
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u32 line_len, ccsidr;
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ccsidr = get_ccsidr();
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line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
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CCSIDR_LINE_SIZE_OFFSET) + 2;
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/* Converting from words to bytes */
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line_len += 2;
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/* converting from log2(linelen) to linelen */
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line_len = 1 << line_len;
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switch (range_op) {
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case ARMV7_DCACHE_CLEAN_INVAL_RANGE:
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v7_dcache_clean_inval_range(start, stop, line_len);
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break;
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case ARMV7_DCACHE_INVAL_RANGE:
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v7_dcache_inval_range(start, stop, line_len);
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break;
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}
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/* DSB to make sure the operation is complete */
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DSB;
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}
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/* Invalidate TLB */
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static void v7_inval_tlb(void)
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{
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/* Invalidate entire unified TLB */
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asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
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/* Invalidate entire data TLB */
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asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
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/* Invalidate entire instruction TLB */
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asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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DSB;
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/* Full system ISB - make sure the instruction stream sees it */
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ISB;
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}
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void invalidate_dcache_all(void)
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{
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v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
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v7_outer_cache_inval_all();
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}
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/*
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* Performs a clean & invalidation of the entire data cache
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* at all levels
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*/
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void flush_dcache_all(void)
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{
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v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
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v7_outer_cache_flush_all();
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}
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/*
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* Invalidates range in all levels of D-cache/unified cache used:
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* Affects the range [start, stop - 1]
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*/
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
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v7_outer_cache_inval_range(start, stop);
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}
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/*
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* Flush range(clean & invalidate) from all levels of D-cache/unified
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* cache used:
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* Affects the range [start, stop - 1]
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*/
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
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v7_outer_cache_flush_range(start, stop);
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}
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void arm_init_before_mmu(void)
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{
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v7_outer_cache_enable();
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invalidate_dcache_all();
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v7_inval_tlb();
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}
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void mmu_page_table_flush(unsigned long start, unsigned long stop)
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{
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flush_dcache_range(start, stop);
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v7_inval_tlb();
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}
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/*
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* Flush range from all levels of d-cache/unified-cache used:
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* Affects the range [start, start + size - 1]
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*/
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void flush_cache(unsigned long start, unsigned long size)
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{
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flush_dcache_range(start, start + size);
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}
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_all(void)
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{
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}
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void flush_dcache_all(void)
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{
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void arm_init_before_mmu(void)
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{
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}
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void flush_cache(unsigned long start, unsigned long size)
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{
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}
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void mmu_page_table_flush(unsigned long start, unsigned long stop)
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{
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}
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void arm_init_domains(void)
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{
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}
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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#ifndef CONFIG_SYS_ICACHE_OFF
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/* Invalidate entire I-cache and branch predictor array */
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void invalidate_icache_all(void)
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{
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/*
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* Invalidate all instruction caches to PoU.
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* Also flushes branch target cache.
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*/
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asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
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/* Invalidate entire branch predictor array */
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asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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DSB;
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/* ISB - make sure the instruction stream sees it */
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ISB;
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}
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#else
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void invalidate_icache_all(void)
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{
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}
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#endif
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/* Stub implementations for outer cache operations */
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__weak void v7_outer_cache_enable(void) {}
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__weak void v7_outer_cache_disable(void) {}
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__weak void v7_outer_cache_flush_all(void) {}
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__weak void v7_outer_cache_inval_all(void) {}
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__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
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__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
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