upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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107 lines
2.7 KiB
107 lines
2.7 KiB
/*
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* Common APIs for EXYNOS based board
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*
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* Copyright (C) 2013 Samsung Electronics
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* Rajeshwari Shinde <rajeshwari.s@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/system.h>
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#define DMC_OFFSET 0x10000
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/*
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* Memory initialization
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*
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* @param reset Reset PHY during initialization.
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*/
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void mem_ctrl_init(int reset);
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/* System Clock initialization */
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void system_clock_init(void);
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/*
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* Init subsystems according to the reset status
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*
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* @return 0 for a normal boot, non-zero for a resume
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*/
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int do_lowlevel_init(void);
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void sdelay(unsigned long);
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enum l2_cache_params {
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CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
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CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
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CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
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CACHE_DATA_RAM_SETUP = (1 << 5),
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CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
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CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
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CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
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CACHE_TAG_RAM_SETUP = (1 << 9),
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CACHE_ECC_AND_PARITY = (1 << 21),
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CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
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};
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#ifndef CONFIG_SYS_L2CACHE_OFF
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/*
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* Configure L2CTLR to get timings that keep us from hanging/crashing.
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*
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* Must be inline here since low_power_start() is called without a
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* stack (!).
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*/
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static inline void configure_l2_ctlr(void)
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{
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uint32_t val;
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mrc_l2_ctlr(val);
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val |= CACHE_TAG_RAM_SETUP |
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CACHE_DATA_RAM_SETUP |
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CACHE_TAG_RAM_LATENCY_2_CYCLES |
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CACHE_DATA_RAM_LATENCY_2_CYCLES;
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if (proid_is_exynos5420() || proid_is_exynos5800()) {
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val |= CACHE_ECC_AND_PARITY |
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CACHE_TAG_RAM_LATENCY_3_CYCLES |
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CACHE_DATA_RAM_LATENCY_3_CYCLES;
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}
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mcr_l2_ctlr(val);
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}
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/*
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* Configure L2ACTLR.
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*
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* Must be inline here since low_power_start() is called without a
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* stack (!).
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*/
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static inline void configure_l2_actlr(void)
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{
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uint32_t val;
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if (proid_is_exynos5420() || proid_is_exynos5800()) {
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mrc_l2_aux_ctlr(val);
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val |= CACHE_ENABLE_FORCE_L2_LOGIC |
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CACHE_DISABLE_CLEAN_EVICT;
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mcr_l2_aux_ctlr(val);
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}
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}
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#endif
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