upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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209 lines
5.1 KiB
209 lines
5.1 KiB
/*
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* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
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*
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* Base on code from TI. Original Notices follow:
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*
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* (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
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*
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* Modified for DA8xx EVM.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Parts are shamelessly stolen from various TI sources, original copyright
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* follows:
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* -----------------------------------------------------------------
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*
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* Copyright (C) 2004 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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* SPDX-License-Identifier: GPL-2.0+
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* ----------------------------------------------------------------------------
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*/
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#include <common.h>
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#include <i2c.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/emac_defs.h>
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#include <asm/arch/pinmux_defs.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <asm/ti-common/davinci_nand.h>
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#include <asm/arch/davinci_misc.h>
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#ifdef CONFIG_DAVINCI_MMC
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#include <mmc.h>
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#include <asm/arch/sdmmc_defs.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static const struct pinmux_resource pinmuxes[] = {
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#ifdef CONFIG_SPI_FLASH
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PINMUX_ITEM(spi0_pins_base),
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PINMUX_ITEM(spi0_pins_scs0),
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PINMUX_ITEM(spi0_pins_ena),
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#endif
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PINMUX_ITEM(uart2_pins_txrx),
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PINMUX_ITEM(i2c0_pins),
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#ifdef CONFIG_USB_DA8XX
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PINMUX_ITEM(usb_pins),
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#endif
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#ifdef CONFIG_USE_NAND
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PINMUX_ITEM(emifa_pins),
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PINMUX_ITEM(emifa_pins_cs0),
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PINMUX_ITEM(emifa_pins_cs2),
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PINMUX_ITEM(emifa_pins_cs3),
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#endif
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#if defined(CONFIG_DRIVER_TI_EMAC)
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PINMUX_ITEM(emac_pins_rmii),
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PINMUX_ITEM(emac_pins_mdio),
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PINMUX_ITEM(emac_pins_rmii_clk_source),
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#endif
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#ifdef CONFIG_DAVINCI_MMC
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PINMUX_ITEM(mmc0_pins_8bit)
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#endif
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};
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static const struct lpsc_resource lpsc[] = {
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{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
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{ DAVINCI_LPSC_SPI0 }, /* Serial Flash */
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{ DAVINCI_LPSC_EMAC }, /* image download */
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{ DAVINCI_LPSC_UART2 }, /* console */
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{ DAVINCI_LPSC_GPIO },
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#ifdef CONFIG_DAVINCI_MMC
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{ DAVINCI_LPSC_MMC_SD },
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#endif
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};
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#ifdef CONFIG_DAVINCI_MMC
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static struct davinci_mmc mmc_sd0 = {
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.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
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.host_caps = MMC_MODE_8BIT,
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.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
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.version = MMC_CTLR_VERSION_2,
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};
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int board_mmc_init(bd_t *bis)
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{
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mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
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printf("%x\n", mmc_sd0.input_clk);
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/* Add slot-0 to mmc subsystem */
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return davinci_mmc_init(bis, &mmc_sd0);
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}
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#endif
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int board_init(void)
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{
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#ifndef CONFIG_USE_IRQ
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irq_init();
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#endif
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#ifdef CONFIG_NAND_DAVINCI
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/* EMIFA 100MHz clock select */
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writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2,
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&davinci_syscfg_regs->cfgchip3);
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/* NAND CS setup */
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writel((DAVINCI_ABCR_WSETUP(0) |
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DAVINCI_ABCR_WSTROBE(2) |
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DAVINCI_ABCR_WHOLD(0) |
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DAVINCI_ABCR_RSETUP(0) |
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DAVINCI_ABCR_RSTROBE(2) |
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DAVINCI_ABCR_RHOLD(0) |
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DAVINCI_ABCR_TA(2) |
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DAVINCI_ABCR_ASIZE_8BIT),
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&davinci_emif_regs->ab2cr);
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#endif
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/* arch number of the board */
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gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/*
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* Power on required peripherals
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* ARM does not have access by default to PSC0 and PSC1
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* assuming here that the DSP bootloader has set the IOPU
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* such that PSC access is available to ARM
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*/
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if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
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return 1;
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/* setup the SUSPSRC for ARM to control emulation suspend */
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writel(readl(&davinci_syscfg_regs->suspsrc) &
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~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
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DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
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DAVINCI_SYSCFG_SUSPSRC_UART2),
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&davinci_syscfg_regs->suspsrc);
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/* configure pinmux settings */
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if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
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return 1;
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/* enable the console UART */
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writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
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DAVINCI_UART_PWREMU_MGMT_UTRST),
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&davinci_uart2_ctrl_regs->pwremu_mgmt);
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return(0);
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}
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#ifdef CONFIG_NAND_DAVINCI
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int board_nand_init(struct nand_chip *nand)
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{
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davinci_nand_init(nand);
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return 0;
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}
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#endif
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#if defined(CONFIG_DRIVER_TI_EMAC)
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#define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */
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/*
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* Initializes on-board ethernet controllers.
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*/
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int board_eth_init(bd_t *bis)
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{
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u_int8_t mac_addr[6];
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u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
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struct eth_device *dev;
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/* Read Ethernet MAC address from EEPROM */
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if (dvevm_read_mac_address(mac_addr))
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/* set address env if not already set */
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davinci_sync_env_enetaddr(mac_addr);
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/* read the address back from env */
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if (!eth_getenv_enetaddr("ethaddr", mac_addr))
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return -1;
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/* enable the Ethernet switch in the 3 port PHY */
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if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
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switch_start_cmd, sizeof(switch_start_cmd))) {
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printf("Ethernet switch start failed!\n");
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return -1;
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}
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/* finally, initialise the driver */
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if (!davinci_emac_initialize()) {
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printf("Error: Ethernet init failed!\n");
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return -1;
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}
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dev = eth_get_dev();
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/* provide the resulting addr to the driver */
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memcpy(dev->enetaddr, mac_addr, 6);
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dev->write_hwaddr(dev);
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return 0;
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}
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#endif /* CONFIG_DRIVER_TI_EMAC */
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