upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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138 lines
3.0 KiB
138 lines
3.0 KiB
/*
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* Voipac PXA270 Support
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/regs-mmc.h>
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#include <asm/arch/pxa.h>
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#include <netdev.h>
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#include <serial.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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/* memory and cpu-speed are setup before relocation */
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/* so we do _nothing_ here */
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/* Arch number of vpac270 */
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gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa0000100;
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return 0;
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}
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int dram_init(void)
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{
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#ifndef CONFIG_ONENAND
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pxa2xx_dram_init();
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#endif
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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#ifdef CONFIG_RAM_256M
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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#endif
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}
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#ifdef CONFIG_CMD_MMC
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int board_mmc_init(bd_t *bis)
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{
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pxa_mmc_register(0);
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return 0;
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}
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#endif
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#ifdef CONFIG_CMD_USB
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int usb_board_init(void)
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{
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writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
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~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
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UHCHR);
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writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
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while (readl(UHCHR) & UHCHR_FSBIR)
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;
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writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
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writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
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/* Clear any OTG Pin Hold */
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if (readl(PSSR) & PSSR_OTGPH)
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writel(readl(PSSR) | PSSR_OTGPH, PSSR);
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writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
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writel(readl(UHCRHDA) | 0x100, UHCRHDA);
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/* Set port power control mask bits, only 3 ports. */
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writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
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/* enable port 2 */
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writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
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UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
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return 0;
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}
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void usb_board_init_fail(void)
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{
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return;
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}
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void usb_board_stop(void)
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{
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writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
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udelay(11);
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writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
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writel(readl(UHCCOMS) | 1, UHCCOMS);
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udelay(10);
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writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
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return;
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}
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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