upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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472 lines
10 KiB
472 lines
10 KiB
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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ulong myflush(void);
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#define FLASH_BANK_SIZE 0x400000 /* 4 MB */
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#define MAIN_SECT_SIZE 0x20000 /* 128 KB */
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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#define CMD_READ_ARRAY 0x00F000F0
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#define CMD_UNLOCK1 0x00AA00AA
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#define CMD_UNLOCK2 0x00550055
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#define CMD_ERASE_SETUP 0x00800080
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#define CMD_ERASE_CONFIRM 0x00300030
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#define CMD_PROGRAM 0x00A000A0
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#define CMD_UNLOCK_BYPASS 0x00200020
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#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
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#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
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#define BIT_ERASE_DONE 0x00800080
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#define BIT_RDY_MASK 0x00800080
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#define BIT_PROGRAM_ERROR 0x00200020
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#define BIT_TIMEOUT 0x80000000 /* our flag */
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#define READY 1
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#define ERR 2
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#define TMO 4
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/*-----------------------------------------------------------------------
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*/
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ulong flash_init(void)
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{
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int i, j;
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ulong size = 0;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
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{
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ulong flashbase = 0;
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flash_info[i].flash_id =
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(AMD_MANUFACT & FLASH_VENDMASK) |
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(AMD_ID_LV160B & FLASH_TYPEMASK);
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flash_info[i].size = FLASH_BANK_SIZE;
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flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
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memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
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if (i == 0)
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flashbase = PHYS_FLASH_1;
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else
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panic("configured to many flash banks!\n");
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for (j = 0; j < flash_info[i].sector_count; j++)
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{
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if (j <= 3)
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{
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/* 1st one is 32 KB */
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if (j == 0)
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{
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flash_info[i].start[j] = flashbase + 0;
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}
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/* 2nd and 3rd are both 16 KB */
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if ((j == 1) || (j == 2))
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{
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flash_info[i].start[j] = flashbase + 0x8000 + (j-1)*0x4000;
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}
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/* 4th 64 KB */
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if (j == 3)
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{
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flash_info[i].start[j] = flashbase + 0x10000;
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}
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}
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else
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{
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flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE;
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}
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}
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size += flash_info[i].size;
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}
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/*
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* Protect monitor and environment sectors
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* Inferno is complicated, it's hardware locked
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*/
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#ifdef CONFIG_INFERNO
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/* first one, 0x00000 to 0x07fff */
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flash_protect(FLAG_PROTECT_SET,
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CFG_FLASH_BASE + 0x00000,
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CFG_FLASH_BASE + 0x08000 - 1,
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&flash_info[0]);
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/* third to 10th, 0x0c000 - 0xdffff */
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flash_protect(FLAG_PROTECT_SET,
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CFG_FLASH_BASE + 0x0c000,
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CFG_FLASH_BASE + 0xe0000 - 1,
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&flash_info[0]);
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#else
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flash_protect(FLAG_PROTECT_SET,
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CFG_FLASH_BASE,
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CFG_FLASH_BASE + monitor_flash_len - 1,
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&flash_info[0]);
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flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
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&flash_info[0]);
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#endif
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return size;
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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switch (info->flash_id & FLASH_VENDMASK)
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{
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case (AMD_MANUFACT & FLASH_VENDMASK):
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printf("AMD: ");
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break;
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default:
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printf("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK)
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{
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case (AMD_ID_LV160B & FLASH_TYPEMASK):
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printf("2x Amd29F160BB (16Mbit)\n");
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break;
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default:
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printf("Unknown Chip Type\n");
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goto Done;
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break;
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}
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printf(" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf(" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; i++)
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{
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if ((i % 5) == 0)
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{
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printf ("\n ");
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}
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printf (" %08lX%s", info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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Done:
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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ulong result;
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int iflag, cflag, prot, sect;
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int rc = ERR_OK;
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int chip1, chip2;
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/* first look for protection bits */
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if (info->flash_id == FLASH_UNKNOWN)
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return ERR_UNKNOWN_FLASH_TYPE;
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if ((s_first < 0) || (s_first > s_last)) {
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return ERR_INVAL;
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}
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if ((info->flash_id & FLASH_VENDMASK) !=
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(AMD_MANUFACT & FLASH_VENDMASK)) {
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return ERR_UNKNOWN_FLASH_VENDOR;
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}
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prot = 0;
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for (sect=s_first; sect<=s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot)
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return ERR_PROTECTED;
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/*
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* Disable interrupts which might cause a timeout
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* here. Remember that our exception vectors are
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* at address 0 in the flash, and we don't want a
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* (ticker) exception to happen while the flash
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* chip is in programming mode.
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*/
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cflag = icache_status();
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icache_disable();
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iflag = disable_interrupts();
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
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{
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printf("Erasing sector %2d ... ", sect);
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/* arm simple, non interrupt dependent timer */
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reset_timer_masked();
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if (info->protect[sect] == 0)
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{ /* not protected */
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vu_long *addr = (vu_long *)(info->start[sect]);
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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*addr = CMD_ERASE_CONFIRM;
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/* wait until flash is ready */
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chip1 = chip2 = 0;
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do
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{
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result = *addr;
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/* check timeout */
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if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
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{
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
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chip1 = TMO;
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break;
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}
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if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
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chip1 = READY;
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if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
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chip1 = ERR;
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if (!chip2 && (result >> 16) & BIT_ERASE_DONE)
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chip2 = READY;
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if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR)
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chip2 = ERR;
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} while (!chip1 || !chip2);
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
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if (chip1 == ERR || chip2 == ERR)
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{
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rc = ERR_PROG_ERROR;
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goto outahere;
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}
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if (chip1 == TMO)
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{
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rc = ERR_TIMOUT;
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goto outahere;
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}
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printf("ok.\n");
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}
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else /* it was protected */
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{
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printf("protected!\n");
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}
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}
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if (ctrlc())
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printf("User Interrupt!\n");
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outahere:
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/* allow flash to settle - wait 10 ms */
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udelay_masked(10000);
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if (iflag)
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enable_interrupts();
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if (cflag)
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icache_enable();
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return rc;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash
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*/
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volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
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{
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vu_long *addr = (vu_long *)dest;
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ulong result;
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int rc = ERR_OK;
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int cflag, iflag;
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int chip1, chip2;
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/*
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* Check if Flash is (sufficiently) erased
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*/
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result = *addr;
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if ((result & data) != data)
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return ERR_NOT_ERASED;
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/*
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* Disable interrupts which might cause a timeout
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* here. Remember that our exception vectors are
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* at address 0 in the flash, and we don't want a
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* (ticker) exception to happen while the flash
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* chip is in programming mode.
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*/
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cflag = icache_status();
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icache_disable();
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iflag = disable_interrupts();
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
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*addr = CMD_PROGRAM;
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*addr = data;
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/* arm simple, non interrupt dependent timer */
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reset_timer_masked();
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/* wait until flash is ready */
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chip1 = chip2 = 0;
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do
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{
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result = *addr;
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/* check timeout */
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if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
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{
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chip1 = ERR | TMO;
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break;
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}
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if (!chip1 && ((result & 0x80) == (data & 0x80)))
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chip1 = READY;
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if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR))
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{
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result = *addr;
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if ((result & 0x80) == (data & 0x80))
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chip1 = READY;
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else
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chip1 = ERR;
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}
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if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16))))
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chip2 = READY;
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if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR))
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{
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result = *addr;
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if ((result & (0x80 << 16)) == (data & (0x80 << 16)))
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chip2 = READY;
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else
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chip2 = ERR;
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}
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} while (!chip1 || !chip2);
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*addr = CMD_READ_ARRAY;
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if (chip1 == ERR || chip2 == ERR || *addr != data)
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rc = ERR_PROG_ERROR;
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if (iflag)
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enable_interrupts();
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if (cflag)
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icache_enable();
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return rc;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash.
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*/
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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{
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ulong cp, wp, data;
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int l;
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int i, rc;
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wp = (addr & ~3); /* get lower word aligned address */
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/*
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* handle unaligned start bytes
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*/
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if ((l = addr - wp) != 0) {
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data = 0;
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for (i=0, cp=wp; i<l; ++i, ++cp) {
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data = (data >> 8) | (*(uchar *)cp << 24);
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}
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for (; i<4 && cnt>0; ++i) {
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data = (data >> 8) | (*src++ << 24);
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--cnt;
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++cp;
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}
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for (; cnt==0 && i<4; ++i, ++cp) {
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data = (data >> 8) | (*(uchar *)cp << 24);
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}
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if ((rc = write_word(info, wp, data)) != 0) {
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return (rc);
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}
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wp += 4;
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}
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/*
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* handle word aligned part
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*/
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while (cnt >= 4) {
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data = *((vu_long*)src);
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if ((rc = write_word(info, wp, data)) != 0) {
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return (rc);
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}
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src += 4;
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wp += 4;
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cnt -= 4;
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}
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if (cnt == 0) {
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return ERR_OK;
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}
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/*
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* handle unaligned tail bytes
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*/
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data = 0;
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for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
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data = (data >> 8) | (*src++ << 24);
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--cnt;
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}
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for (; i<4; ++i, ++cp) {
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data = (data >> 8) | (*(uchar *)cp << 24);
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}
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return write_word(info, wp, data);
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}
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