upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
172 lines
3.2 KiB
172 lines
3.2 KiB
/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/asm.h>
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.text
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.global _interrupt_handler
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_interrupt_handler:
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addi r1, r1, -4
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swi r2, r1, 0
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addi r1, r1, -4
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swi r3, r1, 0
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addi r1, r1, -4
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swi r4, r1, 0
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addi r1, r1, -4
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swi r5, r1, 0
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addi r1, r1, -4
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swi r6, r1, 0
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addi r1, r1, -4
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swi r7, r1, 0
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addi r1, r1, -4
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swi r8, r1, 0
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addi r1, r1, -4
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swi r9, r1, 0
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addi r1, r1, -4
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swi r10, r1, 0
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addi r1, r1, -4
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swi r11, r1, 0
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addi r1, r1, -4
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swi r12, r1, 0
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addi r1, r1, -4
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swi r13, r1, 0
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addi r1, r1, -4
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swi r14, r1, 0
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addi r1, r1, -4
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swi r15, r1, 0
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addi r1, r1, -4
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swi r16, r1, 0
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addi r1, r1, -4
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swi r17, r1, 0
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addi r1, r1, -4
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swi r18, r1, 0
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addi r1, r1, -4
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swi r19, r1, 0
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addi r1, r1, -4
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swi r20, r1, 0
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addi r1, r1, -4
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swi r21, r1, 0
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addi r1, r1, -4
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swi r22, r1, 0
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addi r1, r1, -4
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swi r23, r1, 0
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addi r1, r1, -4
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swi r24, r1, 0
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addi r1, r1, -4
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swi r25, r1, 0
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addi r1, r1, -4
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swi r26, r1, 0
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addi r1, r1, -4
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swi r27, r1, 0
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addi r1, r1, -4
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swi r28, r1, 0
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addi r1, r1, -4
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swi r29, r1, 0
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addi r1, r1, -4
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swi r30, r1, 0
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addi r1, r1, -4
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swi r31, r1, 0
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brlid r15, interrupt_handler
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nop
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nop
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lwi r31, r1, 0
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addi r1, r1, 4
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lwi r30, r1, 0
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addi r1, r1, 4
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lwi r29, r1, 0
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addi r1, r1, 4
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lwi r28, r1, 0
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addi r1, r1, 4
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lwi r27, r1, 0
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addi r1, r1, 4
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lwi r26, r1, 0
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addi r1, r1, 4
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lwi r25, r1, 0
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addi r1, r1, 4
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lwi r24, r1, 0
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addi r1, r1, 4
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lwi r23, r1, 0
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addi r1, r1, 4
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lwi r22, r1, 0
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addi r1, r1, 4
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lwi r21, r1, 0
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addi r1, r1, 4
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lwi r20, r1, 0
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addi r1, r1, 4
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lwi r19, r1, 0
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addi r1, r1, 4
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lwi r18, r1, 0
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addi r1, r1, 4
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lwi r17, r1, 0
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addi r1, r1, 4
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lwi r16, r1, 0
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addi r1, r1, 4
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lwi r15, r1, 0
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addi r1, r1, 4
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lwi r14, r1, 0
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addi r1, r1, 4
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lwi r13, r1, 0
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addi r1, r1, 4
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lwi r12, r1, 0
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addi r1, r1, 4
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lwi r11, r1, 0
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addi r1, r1, 4
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lwi r10, r1, 0
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addi r1, r1, 4
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lwi r9, r1, 0
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addi r1, r1, 4
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lwi r8, r1, 0
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addi r1, r1, 4
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lwi r7, r1, 0
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addi r1, r1, 4
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lwi r6, r1, 0
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addi r1, r1, 4
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lwi r5, r1, 0
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addi r1, r1, 4
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lwi r4, r1, 0
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addi r1, r1, 4
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lwi r3, r1, 0
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addi r1, r1, 4
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lwi r2, r1, 0
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addi r1, r1, 4
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/* enable_interrupt */
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#ifdef XILINX_USE_MSR_INSTR
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msrset r0, 2
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#else
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/* FIXME unstable in stressed mode - two irqs */
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nop
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addi r1, r1, -4
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swi r12, r1, 0
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mfs r12, rmsr
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ori r12, r12, 2
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mts rmsr, r12
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lwi r12, r1, 0
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addi r1, r1, 4
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nop
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#endif
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bra r14
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nop
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nop
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.size _interrupt_handler,.-_interrupt_handler
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