upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
477 lines
12 KiB
477 lines
12 KiB
/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2006
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* MicroSys GmbH
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*
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* Copyright 2012-2013 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <miiphy.h>
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#include <linux/compiler.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#ifdef CONFIG_A4M2K
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#include "is46r16320d.h"
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#else
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#include "mt46v16m16-75.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#if !defined(CONFIG_SYS_RAMBOOT) && \
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(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
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static void sdram_start(int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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long control = SDRAM_CONTROL | hi_addr_bit;
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/* unlock mode register */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
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/* precharge all banks */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
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#ifdef SDRAM_DDR
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/* set mode register: extended mode */
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
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/* set mode register: reset DLL */
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
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#endif
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/* precharge all banks */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
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/* auto refresh */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
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/* set mode register */
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
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/* normal operation */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
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/*
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* Wait a short while for the DLL to lock before accessing
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* the SDRAM
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*/
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udelay(100);
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
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* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
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*/
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phys_size_t initdram(int board_type)
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{
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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uint svr, pvr;
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#if !defined(CONFIG_SYS_RAMBOOT) && \
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(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
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ulong test1, test2;
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/* setup SDRAM chip selects */
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
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out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
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/* setup config registers */
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out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
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out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
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#ifdef SDRAM_DDR
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/* set tap delay */
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out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20))
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dramsize = 0;
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
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0x13 + __builtin_ffs(dramsize >> 20) - 1);
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} else {
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
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}
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#else /* CONFIG_SYS_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
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if (dramsize >= 0x13)
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dramsize = (1 << (dramsize - 0x13)) << 20;
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else
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dramsize = 0;
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
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if (dramsize2 >= 0x13)
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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else
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dramsize2 = 0;
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#endif /* CONFIG_SYS_RAMBOOT */
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/*
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* On MPC5200B we need to set the special configuration delay in the
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
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*
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* "The SDelay should be written to a value of 0x00000004. It is
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* required to account for changes caused by normal wafer processing
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* parameters."
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*/
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svr = get_svr();
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pvr = get_pvr();
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if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
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out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
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return dramsize + dramsize2;
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}
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static void get_revisions(int *failsavelevel, int *digiboardversion,
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int *fpgaversion)
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{
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struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
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u8 val;
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/* read digitalboard-version from TMR[2..4] */
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val = 0;
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val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
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val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
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val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
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*digiboardversion = val;
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/*
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* A4M2K only supports digiboardversion. No failsavelevel and
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* fpgaversion here.
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*/
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#if !defined(CONFIG_A4M2K)
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/*
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* Figure out failsavelevel
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* see ticket dsvk#59
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*/
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*failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
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if (*digiboardversion == 0) {
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*failsavelevel = 1; /* digiboard-version ok */
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/* read fpga-version from TMR[5..7] */
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val = 0;
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val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
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val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
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val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
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*fpgaversion = val;
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if (*fpgaversion == 1)
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*failsavelevel = 2; /* fpga-version ok */
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}
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#endif
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}
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/*
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* This function is called from the SPL U-Boot version for
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* early init stuff, that needs to be done for OS (e.g. Linux)
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* booting. Doing it later in the real U-Boot would not work
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* in case that the SPL U-Boot boots Linux directly.
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*/
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void spl_board_init(void)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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struct mpc5xxx_mmap_ctl *mm =
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(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
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#if defined(CONFIG_A4M2K)
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/* enable CS3 and CS5 (FPGA) */
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setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
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#else
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int digiboardversion;
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int failsavelevel;
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int fpgaversion;
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u32 val;
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get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
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val = in_be32(&mm->ipbi_ws_ctrl);
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/* first clear bits 19..21 (CS3...5) */
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val &= ~((1 << 19) | (1 << 20) | (1 << 21));
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if (failsavelevel == 2) {
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/* FPGA ok */
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val |= (1 << 19) | (1 << 21);
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}
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if (failsavelevel >= 1) {
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/* at least digiboard-version ok */
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val |= (1 << 20);
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}
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/* And write new value back to register */
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out_be32(&mm->ipbi_ws_ctrl, val);
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/* Setup pin multiplexing */
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if (failsavelevel == 2) {
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/* fpga-version ok */
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#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2)
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out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2);
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#endif
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} else if (failsavelevel == 1) {
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/* digiboard-version ok - fpga not */
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#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1)
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out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1);
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#endif
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} else {
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/* full failsave-mode */
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#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
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out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
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#endif
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}
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#endif
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/*
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* Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
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* ticket #60
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*
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* MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
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* set bit 0(msb) to 1
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*/
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setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN);
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#if defined(CONFIG_A4M2K)
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/* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
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/* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
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gpio->simple_ddr |= 1 << (31 - 15);
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gpio->simple_ddr |= 1 << (31 - 14);
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gpio->simple_ddr |= 1 << (31 - 13);
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gpio->simple_ddr |= 1 << (31 - 12);
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/* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
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gpio->simple_gpioe |= 1 << (31 - 15);
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gpio->simple_gpioe |= 1 << (31 - 14);
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gpio->simple_gpioe |= 1 << (31 - 13);
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gpio->simple_gpioe |= 1 << (31 - 12);
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/* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
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/* set PSC2[0..2] (STSLED[0..2]) direction to output */
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gpio->simple_ddr |= 1 << (31 - 27);
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gpio->simple_ddr |= 1 << (31 - 26);
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gpio->simple_ddr |= 1 << (31 - 25);
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/* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
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gpio->simple_gpioe |= 1 << (31 - 27);
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gpio->simple_gpioe |= 1 << (31 - 26);
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gpio->simple_gpioe |= 1 << (31 - 25);
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/* Setup PSC6[2] as MRST2 self reset GPIO output */
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/* set PSC6[2]/IRDA_TX (MRST2) direction to output */
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gpio->simple_ddr |= 1 << (31 - 3);
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/* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
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gpio->simple_ode |= 1 << (31 - 3);
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/* set PSC6[2]/IRDA_TX (MRST2) output as default high */
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gpio->simple_dvo |= 1 << (31 - 3);
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/* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
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gpio->simple_gpioe |= 1 << (31 - 3);
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/* Setup PSC6[3] as HARNSSCD harness code GPIO input */
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/* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
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gpio->simple_ddr |= 0 << (31 - 2);
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/* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
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gpio->simple_gpioe |= 1 << (31 - 2);
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#else
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/* setup GPIOs for status-leds if needed - see ticket #57 */
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if (failsavelevel > 0) {
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/* digiboard-version is OK */
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/* LED is LOW ACTIVE - so deactivate by set output to 1 */
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gpio->simple_dvo |= 1 << (31 - 12);
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gpio->simple_dvo |= 1 << (31 - 13);
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/* set GPIO direction to output */
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gpio->simple_ddr |= 1 << (31 - 12);
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gpio->simple_ddr |= 1 << (31 - 13);
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/* open drain config is set to "normal output" at reset */
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/* gpio->simple_ode &=~ ( 1 << (31-12) ); */
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/* gpio->simple_ode &=~ ( 1 << (31-13) ); */
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/* enable as GPIO */
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gpio->simple_gpioe |= 1 << (31 - 12);
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gpio->simple_gpioe |= 1 << (31 - 13);
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}
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/* setup fpga irq - see ticket #65 */
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if (failsavelevel > 1) {
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/*
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* The main irq initialisation is done in interrupts.c
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* mpc5xxx_init_irq
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*/
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struct mpc5xxx_intr *intr =
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(struct mpc5xxx_intr *)(MPC5XXX_ICTL);
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setbits_be32(&intr->ctrl, 0x08C01801);
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/*
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* The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
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* already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
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*/
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}
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#endif
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}
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int checkboard(void)
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{
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int digiboardversion;
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int failsavelevel;
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int fpgaversion;
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get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
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#ifdef CONFIG_A4M2K
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puts("Board: A4M2K\n");
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printf(" digiboard IO version %u\n", digiboardversion);
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#else
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puts("Board: A3M071\n");
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printf("Rev: failsave level %u\n", failsavelevel);
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printf(" digiboard IO version %u\n", digiboardversion);
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if (failsavelevel > 0) /* only if fpga-version red */
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printf(" fpga IO version %u\n", fpgaversion);
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#endif
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return 0;
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}
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/* miscellaneous platform dependent initialisations */
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int misc_init_r(void)
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{
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/* adjust flash start and offset to detected values */
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gd->bd->bi_flashstart = flash_info[0].start[0];
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gd->bd->bi_flashoffset = 0;
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/* adjust mapping */
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out_be32((void *)MPC5XXX_BOOTCS_START,
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START_REG(gd->bd->bi_flashstart));
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out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
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out_be32((void *)MPC5XXX_BOOTCS_STOP,
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STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
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out_be32((void *)MPC5XXX_CS0_STOP,
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STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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return 0;
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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#ifdef CONFIG_SPL_OS_BOOT
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/*
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* A3M071 specific implementation of spl_start_uboot()
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*
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* RETURN
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* 0 if booting into OS is selected (default)
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* 1 if booting into U-Boot is selected
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*/
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int spl_start_uboot(void)
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{
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char s[8];
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env_init();
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getenv_f("boot_os", s, sizeof(s));
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if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' ||
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*s == 't' || *s == 'T'))
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return 0;
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return 1;
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}
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#endif
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#if defined(CONFIG_HW_WATCHDOG)
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static int watchdog_toggle;
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void hw_watchdog_reset(void)
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{
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int val;
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/*
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* Check if watchdog is enabled via user command
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*/
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if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) {
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/* Set direction to output */
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setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN);
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/*
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* Toggle watchdog output
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*/
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val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
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CONFIG_WDOG_GPIO_PIN);
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if (val) {
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clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
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CONFIG_WDOG_GPIO_PIN);
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} else {
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setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
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CONFIG_WDOG_GPIO_PIN);
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}
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}
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}
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int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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if (argc != 2)
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goto usage;
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if (strncmp(argv[1], "on", 2) == 0)
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watchdog_toggle = 1;
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else if (strncmp(argv[1], "off", 3) == 0)
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watchdog_toggle = 0;
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else
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goto usage;
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return 0;
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usage:
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printf("Usage: wdogtoggle %s\n", cmdtp->usage);
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return 1;
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}
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U_BOOT_CMD(
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wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle,
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"toggle GPIO pin to service watchdog",
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"[on/off] - Switch watchdog toggling via GPIO pin on/off"
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);
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#endif
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