upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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422 lines
12 KiB
422 lines
12 KiB
/*
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* Copyright (C) 2014 Soeren Moch <smoch@web.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/sata.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/video.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_SRE_SLOW)
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
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#ifdef CONFIG_SYS_I2C
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/* I2C1, SGTL5000 */
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static struct i2c_pads_info i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
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.gp = IMX_GPIO_NR(5, 27)
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},
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.sda = {
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.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
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.gp = IMX_GPIO_NR(5, 26)
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}
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};
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/* I2C2 HDMI */
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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/* I2C3, CON11, DS1307, PCIe_SMB */
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static struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
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.gp = IMX_GPIO_NR(1, 3)
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
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.gp = IMX_GPIO_NR(1, 6)
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}
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};
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#endif /* CONFIG_SYS_I2C */
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart2_pads[] = {
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MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/* AR8035 PHY Reset */
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MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const pcie_pads[] = {
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/* W_DISABLE# */
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MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
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/* PERST# */
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MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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int dram_init(void)
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{
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gd->ram_size = 2048ul * 1024 * 1024;
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return 0;
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}
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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/* Reset AR8035 PHY */
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gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
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udelay(500);
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gpio_set_value(IMX_GPIO_NR(1, 25), 1);
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}
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static void setup_pcie(void)
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{
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imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
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}
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static struct fsl_esdhc_cfg usdhc_cfg[3] = {
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{USDHC2_BASE_ADDR},
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{USDHC3_BASE_ADDR},
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{USDHC4_BASE_ADDR},
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};
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
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#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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break;
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case USDHC3_BASE_ADDR:
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ret = !gpio_get_value(USDHC3_CD_GPIO);
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break;
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case USDHC4_BASE_ADDR:
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ret = 1; /* eMMC/uSDHC4 is always present */
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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/*
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* (U-Boot device node) (Physical Port)
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* mmc0 SD2
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* mmc1 SD3
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* mmc2 eMMC
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*/
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int i, ret;
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(
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usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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gpio_direction_input(USDHC2_CD_GPIO);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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gpio_direction_input(USDHC3_CD_GPIO);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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break;
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case 2:
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imx_iomux_v3_setup_multiple_pads(
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
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usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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break;
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default:
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printf("Warning: you configured more USDHC controllers"
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"(%d) then supported by the board (%d)\n",
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i + 1, CONFIG_SYS_FSL_USDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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/* set environment device to boot device when booting from SD */
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int board_mmc_get_env_dev(int devno)
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{
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return devno - 1;
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}
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int board_mmc_get_env_part(int devno)
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{
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return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
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}
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#endif /* CONFIG_FSL_ESDHC */
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#ifdef CONFIG_VIDEO_IPUV3
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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struct display_info_t const displays[] = {{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = do_enable_hdmi,
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.mode = {
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.name = "HDMI",
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/* 1024x768@60Hz (VESA)*/
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15384,
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.left_margin = 160,
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.right_margin = 24,
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.upper_margin = 29,
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.lower_margin = 3,
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.hsync_len = 136,
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.vsync_len = 6,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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static void setup_display(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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s32 timeout = 100000;
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enable_ipu_clock();
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imx_setup_hdmi();
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/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
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reg = readl(&ccm->analog_pll_video);
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reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
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writel(reg, &ccm->analog_pll_video);
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reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
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reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
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writel(reg, &ccm->analog_pll_video);
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writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
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writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
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reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
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writel(reg, &ccm->analog_pll_video);
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while (timeout--)
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if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
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break;
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if (timeout < 0)
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printf("Warning: video pll lock timeout!\n");
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reg = readl(&ccm->analog_pll_video);
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reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
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reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
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writel(reg, &ccm->analog_pll_video);
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/* gate ipu1_di0_clk */
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reg = readl(&ccm->CCGR3);
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reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
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writel(reg, &ccm->CCGR3);
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/* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
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reg = readl(&ccm->chsccdr);
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reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
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MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
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(6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
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(0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &ccm->chsccdr);
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/* enable ipu1_di0_clk */
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reg = readl(&ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
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writel(reg, &ccm->CCGR3);
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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int board_eth_init(bd_t *bis)
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{
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setup_iomux_enet();
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setup_pcie();
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return cpu_eth_init(bis);
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
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{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
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/* 8 bit bus width */
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{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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#ifdef CONFIG_USB_EHCI_MX6
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static iomux_v3_cfg_t const usb_otg_pads[] = {
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MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
#endif
|
|
|
|
int board_init(void)
|
|
{
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
|
|
|
#ifdef CONFIG_VIDEO_IPUV3
|
|
setup_display();
|
|
#endif
|
|
#ifdef CONFIG_SYS_I2C
|
|
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
|
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
|
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
|
#endif
|
|
#ifdef CONFIG_DWC_AHSATA
|
|
setup_sata();
|
|
#endif
|
|
#ifdef CONFIG_CMD_BMODE
|
|
add_board_boot_modes(board_boot_modes);
|
|
#endif
|
|
#ifdef CONFIG_USB_EHCI_MX6
|
|
imx_iomux_v3_setup_multiple_pads(
|
|
usb_otg_pads, ARRAY_SIZE(usb_otg_pads));
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: TBS2910 Matrix ARM mini PC\n");
|
|
return 0;
|
|
}
|
|
|