upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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96 lines
1.6 KiB
96 lines
1.6 KiB
/*
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* (C) Copyright 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <rtc.h>
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int dm_rtc_get(struct udevice *dev, struct rtc_time *time)
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{
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struct rtc_ops *ops = rtc_get_ops(dev);
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assert(ops);
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if (!ops->get)
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return -ENOSYS;
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return ops->get(dev, time);
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}
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int dm_rtc_set(struct udevice *dev, struct rtc_time *time)
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{
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struct rtc_ops *ops = rtc_get_ops(dev);
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assert(ops);
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if (!ops->set)
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return -ENOSYS;
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return ops->set(dev, time);
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}
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int dm_rtc_reset(struct udevice *dev)
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{
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struct rtc_ops *ops = rtc_get_ops(dev);
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assert(ops);
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if (!ops->reset)
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return -ENOSYS;
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return ops->reset(dev);
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}
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int rtc_read8(struct udevice *dev, unsigned int reg)
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{
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struct rtc_ops *ops = rtc_get_ops(dev);
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assert(ops);
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if (!ops->read8)
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return -ENOSYS;
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return ops->read8(dev, reg);
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}
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int rtc_write8(struct udevice *dev, unsigned int reg, int val)
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{
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struct rtc_ops *ops = rtc_get_ops(dev);
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assert(ops);
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if (!ops->write8)
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return -ENOSYS;
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return ops->write8(dev, reg, val);
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}
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int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep)
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{
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u32 value = 0;
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int ret;
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int i;
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for (i = 0; i < sizeof(value); i++) {
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ret = rtc_read8(dev, reg + i);
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if (ret < 0)
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return ret;
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value |= ret << (i << 3);
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}
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*valuep = value;
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return 0;
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}
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int rtc_write32(struct udevice *dev, unsigned int reg, u32 value)
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{
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int i, ret;
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for (i = 0; i < sizeof(value); i++) {
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ret = rtc_write8(dev, reg + i, (value >> (i << 3)) & 0xff);
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if (ret)
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return ret;
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}
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return 0;
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}
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UCLASS_DRIVER(rtc) = {
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.name = "rtc",
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.id = UCLASS_RTC,
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};
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