upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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232 lines
6.4 KiB
232 lines
6.4 KiB
/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Jaehoon Chung <jh80.chung@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DWMMC_HW_H
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#define __DWMMC_HW_H
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#include <asm/io.h>
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#include <mmc.h>
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#define DWMCI_CTRL 0x000
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#define DWMCI_PWREN 0x004
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#define DWMCI_CLKDIV 0x008
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#define DWMCI_CLKSRC 0x00C
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#define DWMCI_CLKENA 0x010
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#define DWMCI_TMOUT 0x014
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#define DWMCI_CTYPE 0x018
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#define DWMCI_BLKSIZ 0x01C
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#define DWMCI_BYTCNT 0x020
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#define DWMCI_INTMASK 0x024
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#define DWMCI_CMDARG 0x028
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#define DWMCI_CMD 0x02C
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#define DWMCI_RESP0 0x030
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#define DWMCI_RESP1 0x034
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#define DWMCI_RESP2 0x038
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#define DWMCI_RESP3 0x03C
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#define DWMCI_MINTSTS 0x040
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#define DWMCI_RINTSTS 0x044
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#define DWMCI_STATUS 0x048
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#define DWMCI_FIFOTH 0x04C
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#define DWMCI_CDETECT 0x050
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#define DWMCI_WRTPRT 0x054
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#define DWMCI_GPIO 0x058
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#define DWMCI_TCMCNT 0x05C
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#define DWMCI_TBBCNT 0x060
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#define DWMCI_DEBNCE 0x064
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#define DWMCI_USRID 0x068
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#define DWMCI_VERID 0x06C
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#define DWMCI_HCON 0x070
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#define DWMCI_UHS_REG 0x074
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#define DWMCI_BMOD 0x080
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#define DWMCI_PLDMND 0x084
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#define DWMCI_DBADDR 0x088
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#define DWMCI_IDSTS 0x08C
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#define DWMCI_IDINTEN 0x090
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#define DWMCI_DSCADDR 0x094
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#define DWMCI_BUFADDR 0x098
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#define DWMCI_DATA 0x200
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/* Interrupt Mask register */
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#define DWMCI_INTMSK_ALL 0xffffffff
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#define DWMCI_INTMSK_RE (1 << 1)
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#define DWMCI_INTMSK_CDONE (1 << 2)
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#define DWMCI_INTMSK_DTO (1 << 3)
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#define DWMCI_INTMSK_TXDR (1 << 4)
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#define DWMCI_INTMSK_RXDR (1 << 5)
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#define DWMCI_INTMSK_DCRC (1 << 7)
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#define DWMCI_INTMSK_RTO (1 << 8)
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#define DWMCI_INTMSK_DRTO (1 << 9)
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#define DWMCI_INTMSK_HTO (1 << 10)
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#define DWMCI_INTMSK_FRUN (1 << 11)
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#define DWMCI_INTMSK_HLE (1 << 12)
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#define DWMCI_INTMSK_SBE (1 << 13)
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#define DWMCI_INTMSK_ACD (1 << 14)
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#define DWMCI_INTMSK_EBE (1 << 15)
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/* Raw interrupt Regsiter */
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#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
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DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
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#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
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/* CTRL register */
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#define DWMCI_CTRL_RESET (1 << 0)
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#define DWMCI_CTRL_FIFO_RESET (1 << 1)
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#define DWMCI_CTRL_DMA_RESET (1 << 2)
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#define DWMCI_DMA_EN (1 << 5)
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#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
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#define DWMCI_IDMAC_EN (1 << 25)
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#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
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DWMCI_CTRL_DMA_RESET)
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/* CMD register */
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#define DWMCI_CMD_RESP_EXP (1 << 6)
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#define DWMCI_CMD_RESP_LENGTH (1 << 7)
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#define DWMCI_CMD_CHECK_CRC (1 << 8)
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#define DWMCI_CMD_DATA_EXP (1 << 9)
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#define DWMCI_CMD_RW (1 << 10)
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#define DWMCI_CMD_SEND_STOP (1 << 12)
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#define DWMCI_CMD_ABORT_STOP (1 << 14)
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#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
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#define DWMCI_CMD_UPD_CLK (1 << 21)
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#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
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#define DWMCI_CMD_START (1 << 31)
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/* CLKENA register */
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#define DWMCI_CLKEN_ENABLE (1 << 0)
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#define DWMCI_CLKEN_LOW_PWR (1 << 16)
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/* Card-type registe */
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#define DWMCI_CTYPE_1BIT 0
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#define DWMCI_CTYPE_4BIT (1 << 0)
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#define DWMCI_CTYPE_8BIT (1 << 16)
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/* Status Register */
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#define DWMCI_BUSY (1 << 9)
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#define DWMCI_FIFO_MASK 0x1ff
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#define DWMCI_FIFO_SHIFT 17
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/* FIFOTH Register */
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#define MSIZE(x) ((x) << 28)
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#define RX_WMARK(x) ((x) << 16)
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#define TX_WMARK(x) (x)
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#define RX_WMARK_SHIFT 16
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#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
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#define DWMCI_IDMAC_OWN (1 << 31)
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#define DWMCI_IDMAC_CH (1 << 4)
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#define DWMCI_IDMAC_FS (1 << 3)
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#define DWMCI_IDMAC_LD (1 << 2)
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/* Bus Mode Register */
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#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
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#define DWMCI_BMOD_IDMAC_FB (1 << 1)
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#define DWMCI_BMOD_IDMAC_EN (1 << 7)
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/* UHS register */
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#define DWMCI_DDR_MODE (1 << 16)
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/* quirks */
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#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
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/**
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* struct dwmci_host - Information about a designware MMC host
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*
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* @name: Device name
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* @ioaddr: Base I/O address of controller
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* @quirks: Quick flags - see DWMCI_QUIRK_...
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* @caps: Capabilities - see MMC_MODE_...
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* @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
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* @div: Arbitrary clock divider value for use by controller
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* @dev_index: Arbitrary device index for use by controller
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* @dev_id: Arbitrary device ID for use by controller
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* @buswidth: Bus width in bits (8 or 4)
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* @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
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* @mmc: Pointer to generic MMC structure for this device
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* @priv: Private pointer for use by controller
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*/
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struct dwmci_host {
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const char *name;
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void *ioaddr;
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unsigned int quirks;
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unsigned int caps;
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unsigned int version;
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unsigned int clock;
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unsigned int bus_hz;
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unsigned int div;
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int dev_index;
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int dev_id;
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int buswidth;
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u32 fifoth_val;
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struct mmc *mmc;
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void *priv;
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void (*clksel)(struct dwmci_host *host);
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void (*board_init)(struct dwmci_host *host);
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/**
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* Get / set a particular MMC clock frequency
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*
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* This is used to request the current clock frequency of the clock
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* that drives the DWMMC peripheral. The caller will then use this
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* information to work out the divider it needs to achieve the
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* required MMC bus clock frequency. If you want to handle the
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* clock external to DWMMC, use @freq to select the frequency and
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* return that value too. Then DWMMC will put itself in bypass mode.
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*
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* @host: DWMMC host
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* @freq: Frequency the host is trying to achieve
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*/
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unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
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#ifndef CONFIG_BLK
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struct mmc_config cfg;
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#endif
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/* use fifo mode to read and write data */
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bool fifo_mode;
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};
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struct dwmci_idmac {
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u32 flags;
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u32 cnt;
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u32 addr;
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u32 next_addr;
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} __aligned(ARCH_DMA_MINALIGN);
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static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
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{
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writel(val, host->ioaddr + reg);
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}
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static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
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{
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writew(val, host->ioaddr + reg);
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}
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static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
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{
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writeb(val, host->ioaddr + reg);
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}
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static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
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{
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return readl(host->ioaddr + reg);
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}
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static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
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{
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return readw(host->ioaddr + reg);
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}
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static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
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{
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return readb(host->ioaddr + reg);
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}
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void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
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uint caps, u32 max_clk, u32 min_clk);
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int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
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int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
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#endif /* __DWMMC_HW_H */
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