upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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350 lines
9.7 KiB
350 lines
9.7 KiB
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*/
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#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
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#include <common.h>
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#include <errno.h>
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#include <dm/of_access.h>
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#include <dm/ofnode.h>
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#include "../xusb-padctl-common.h"
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#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
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#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
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enum tegra124_function {
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TEGRA124_FUNC_SNPS,
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TEGRA124_FUNC_XUSB,
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TEGRA124_FUNC_UART,
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TEGRA124_FUNC_PCIE,
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TEGRA124_FUNC_USB3,
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TEGRA124_FUNC_SATA,
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TEGRA124_FUNC_RSVD,
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};
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static const char *const tegra124_functions[] = {
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"snps",
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"xusb",
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"uart",
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"pcie",
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"usb3",
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"sata",
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"rsvd",
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};
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static const unsigned int tegra124_otg_functions[] = {
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TEGRA124_FUNC_SNPS,
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TEGRA124_FUNC_XUSB,
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TEGRA124_FUNC_UART,
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TEGRA124_FUNC_RSVD,
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};
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static const unsigned int tegra124_usb_functions[] = {
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TEGRA124_FUNC_SNPS,
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TEGRA124_FUNC_XUSB,
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};
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static const unsigned int tegra124_pci_functions[] = {
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TEGRA124_FUNC_PCIE,
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TEGRA124_FUNC_USB3,
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TEGRA124_FUNC_SATA,
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TEGRA124_FUNC_RSVD,
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};
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#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
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{ \
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.name = _name, \
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.offset = _offset, \
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.shift = _shift, \
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.mask = _mask, \
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.iddq = _iddq, \
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.num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
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.funcs = tegra124_##_funcs##_functions, \
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}
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static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
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TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
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TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
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TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
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TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
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TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
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TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
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TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
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TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
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TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
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TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
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TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
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TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
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};
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static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
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{
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u32 value;
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if (padctl->enable++ > 0)
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return 0;
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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return 0;
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}
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static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
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{
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u32 value;
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if (padctl->enable == 0) {
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pr_err("unbalanced enable/disable");
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return 0;
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}
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if (--padctl->enable > 0)
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return 0;
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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return 0;
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}
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static int phy_prepare(struct tegra_xusb_phy *phy)
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{
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return tegra_xusb_padctl_enable(phy->padctl);
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}
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static int phy_unprepare(struct tegra_xusb_phy *phy)
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{
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return tegra_xusb_padctl_disable(phy->padctl);
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}
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static int pcie_phy_enable(struct tegra_xusb_phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy->padctl;
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int err = -ETIMEDOUT;
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unsigned long start;
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
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value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
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XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
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XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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start = get_timer(0);
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while (get_timer(start) < 50) {
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
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err = 0;
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break;
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}
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}
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return err;
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}
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static int pcie_phy_disable(struct tegra_xusb_phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy->padctl;
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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return 0;
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}
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static int sata_phy_enable(struct tegra_xusb_phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy->padctl;
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int err = -ETIMEDOUT;
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unsigned long start;
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
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value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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start = get_timer(0);
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while (get_timer(start) < 50) {
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
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err = 0;
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break;
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}
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}
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return err;
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}
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static int sata_phy_disable(struct tegra_xusb_phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy->padctl;
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
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value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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return 0;
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}
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static const struct tegra_xusb_phy_ops pcie_phy_ops = {
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.prepare = phy_prepare,
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.enable = pcie_phy_enable,
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.disable = pcie_phy_disable,
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.unprepare = phy_unprepare,
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};
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static const struct tegra_xusb_phy_ops sata_phy_ops = {
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.prepare = phy_prepare,
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.enable = sata_phy_enable,
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.disable = sata_phy_disable,
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.unprepare = phy_unprepare,
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};
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static struct tegra_xusb_phy tegra124_phys[] = {
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{
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.type = TEGRA_XUSB_PADCTL_PCIE,
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.ops = &pcie_phy_ops,
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.padctl = &padctl,
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},
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{
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.type = TEGRA_XUSB_PADCTL_SATA,
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.ops = &sata_phy_ops,
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.padctl = &padctl,
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},
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};
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static const struct tegra_xusb_padctl_soc tegra124_socdata = {
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.lanes = tegra124_lanes,
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.num_lanes = ARRAY_SIZE(tegra124_lanes),
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.functions = tegra124_functions,
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.num_functions = ARRAY_SIZE(tegra124_functions),
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.phys = tegra124_phys,
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.num_phys = ARRAY_SIZE(tegra124_phys),
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};
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void tegra_xusb_padctl_init(void)
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{
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ofnode nodes[1];
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int count = 0;
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int ret;
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debug("%s: start\n", __func__);
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if (of_live_active()) {
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struct device_node *np = of_find_compatible_node(NULL, NULL,
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"nvidia,tegra124-xusb-padctl");
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debug("np=%p\n", np);
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if (np) {
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nodes[0] = np_to_ofnode(np);
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count = 1;
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}
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} else {
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int node_offsets[1];
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int i;
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count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
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COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
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node_offsets, ARRAY_SIZE(node_offsets));
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for (i = 0; i < count; i++)
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nodes[i] = offset_to_ofnode(node_offsets[i]);
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}
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ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata);
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debug("%s: done, ret=%d\n", __func__, ret);
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}
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