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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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static void wait_init_complete(void)
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{
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u32 val;
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do {
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mfsdram(SDRAM0_MCSTS, val);
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} while (!(val & 0x80000000));
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}
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/*
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* phys_size_t initdram(int board_type)
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*
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* As the name already indicates, this function is called very early
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* from start.S and configures the SDRAM with fixed values. This is needed,
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* since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
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* not enough free space to implement the complete I2C SPD DDR autodetection
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* routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
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* when booting from NAND flash.
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*
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* Note:
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* As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
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* DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
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* modules are still plugged in. So it is recommended to remove the DIMM
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* modules while using the NAND booting code with the fixed SDRAM setup!
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*/
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phys_size_t initdram(int board_type)
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{
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/*
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* Soft-reset SDRAM controller.
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*/
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mtsdr(SDR0_SRST, SDR0_SRST_DMC);
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mtsdr(SDR0_SRST, 0x00000000);
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/*
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* Disable memory controller.
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*/
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mtsdram(SDRAM0_CFG0, 0x00000000);
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/*
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* Setup some default
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*/
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mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
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mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
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mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram(SDRAM0_B0CR, 0x00082001);
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mtsdram(SDRAM0_TR0, 0x41094012);
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mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
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mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8<EFBFBD>s @ 133MHz PLB */
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mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
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/*
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* Enable the controller, then wait for DCEN to complete
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*/
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mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
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wait_init_complete();
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return CONFIG_SYS_MBYTES_SDRAM << 20;
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}
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