upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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272 lines
6.6 KiB
272 lines
6.6 KiB
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2005-2007
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <malloc.h>
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#include <pci.h>
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#include <i2c.h>
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#include <fpga.h>
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#include <environment.h>
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#include <fdt_support.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include "fpga.h"
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#include "mvbc_p.h"
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#include "../common/mv_common.h"
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#define SDRAM_MODE 0x00CD0000
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#define SDRAM_CONTROL 0x504F0000
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#define SDRAM_CONFIG1 0xD2322800
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#define SDRAM_CONFIG2 0x8AD70000
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DECLARE_GLOBAL_DATA_PTR;
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static void sdram_start (int hi_addr)
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{
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long hi_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
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/* precharge all banks */
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out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
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/* precharge all banks */
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out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
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/* auto refresh */
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out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
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/* set mode register */
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out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
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/* normal operation */
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out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
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}
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phys_addr_t initdram (int board_type)
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{
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ulong dramsize = 0;
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ulong test1,
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test2;
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/* setup SDRAM chip selects */
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out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
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/* setup config registers */
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out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
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out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else
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dramsize = test2;
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if (dramsize < (1 << 20))
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dramsize = 0;
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if (dramsize > 0)
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out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
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__builtin_ffs(dramsize >> 20) - 1);
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else
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out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
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return dramsize;
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}
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void mvbc_init_gpio(void)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
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printf("Ports : 0x%08x\n", gpio->port_config);
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printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
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out_be32(&gpio->simple_ddr, SIMPLE_DDR);
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out_be32(&gpio->simple_dvo, SIMPLE_DVO);
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out_be32(&gpio->simple_ode, SIMPLE_ODE);
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out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
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out_8(&gpio->sint_ode, SINT_ODE);
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out_8(&gpio->sint_ddr, SINT_DDR);
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out_8(&gpio->sint_dvo, SINT_DVO);
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out_8(&gpio->sint_inten, SINT_INTEN);
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out_be16(&gpio->sint_itype, SINT_ITYPE);
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out_8(&gpio->sint_gpioe, SINT_GPIOEN);
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out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
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out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
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out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
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out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
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printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
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printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
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}
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int misc_init_r(void)
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{
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char *s = getenv("reset_env");
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if (!s) {
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if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
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return 0;
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udelay(50000);
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if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
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return 0;
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udelay(50000);
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if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
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return 0;
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}
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printf(" === FACTORY RESET ===\n");
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mv_reset_environment();
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saveenv();
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return -1;
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}
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int checkboard(void)
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{
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mvbc_init_gpio();
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printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
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return 0;
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}
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void flash_preinit(void)
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{
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/*
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* Now, when we are in RAM, enable flash write
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* access for detection process.
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* Note that CS_BOOT cannot be cleared when
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* executing in flash.
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*/
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clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
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}
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void flash_afterinit(ulong size)
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{
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out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
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size));
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out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
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size));
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out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
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size));
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out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
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size));
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}
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void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned char line = 0xff;
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char *s = getenv("pci_latency");
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u32 base;
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u8 val = 0;
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if (s)
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val = simple_strtoul(s, NULL, 16);
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if (PCI_BUS(dev) == 0) {
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switch (PCI_DEV (dev)) {
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case 0xa: /* FPGA */
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line = 3;
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pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
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printf("found FPGA - enable arbitration\n");
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writel(0x03, (u32*)(base + 0x80c0));
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writel(0xf0, (u32*)(base + 0x8080));
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if (val)
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
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break;
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case 0xb: /* LAN */
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line = 2;
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if (val)
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
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break;
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case 0x1a:
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break;
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default:
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printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
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break;
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}
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
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}
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}
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struct pci_controller hose = {
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fixup_irq:pci_mvbc_fixup_irq
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};
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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mvbc_p_init_fpga();
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mv_load_fpga();
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pci_mpc5xxx_init(&hose);
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}
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void show_boot_progress(int val)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
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switch(val) {
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case 0: /* FPGA ok */
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setbits_be32(&gpio->simple_dvo, LED_G0);
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break;
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case 65:
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setbits_be32(&gpio->simple_dvo, LED_G1);
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break;
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case 12:
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setbits_be32(&gpio->simple_dvo, LED_Y);
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break;
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case 15:
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setbits_be32(&gpio->simple_dvo, LED_R);
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break;
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default:
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break;
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}
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
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}
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis); /* Built in FEC comes first */
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return pci_eth_init(bis);
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}
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