upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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83 lines
2.5 KiB
83 lines
2.5 KiB
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_AVR32_CACHEFLUSH_H
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#define __ASM_AVR32_CACHEFLUSH_H
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/*
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* Invalidate any cacheline containing virtual address vaddr without
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* writing anything back to memory.
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*
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* Note that this function may corrupt unrelated data structures when
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* applied on buffers that are not cacheline aligned in both ends.
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*/
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static inline void dcache_invalidate_line(volatile void *vaddr)
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{
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asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory");
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}
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/*
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* Make sure any cacheline containing virtual address vaddr is written
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* to memory.
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*/
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static inline void dcache_clean_line(volatile void *vaddr)
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{
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asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory");
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}
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/*
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* Make sure any cacheline containing virtual address vaddr is written
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* to memory and then invalidate it.
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*/
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static inline void dcache_flush_line(volatile void *vaddr)
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{
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asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory");
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}
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/*
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* Invalidate any instruction cacheline containing virtual address
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* vaddr.
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*/
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static inline void icache_invalidate_line(volatile void *vaddr)
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{
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asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory");
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}
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/*
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* Applies the above functions on all lines that are touched by the
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* specified virtual address range.
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*/
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void dcache_invalidate_range(volatile void *start, size_t len);
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void dcache_clean_range(volatile void *start, size_t len);
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void dcache_flush_range(volatile void *start, size_t len);
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void icache_invalidate_range(volatile void *start, size_t len);
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static inline void dcache_flush_unlocked(void)
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{
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asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory");
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}
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/*
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* Make sure any pending writes are completed before continuing.
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*/
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#define sync_write_buffer() asm volatile("sync 0" : : : "memory")
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#endif /* __ASM_AVR32_CACHEFLUSH_H */
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