upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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581 lines
15 KiB
581 lines
15 KiB
/*
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* From coreboot southbridge/intel/bd82x6x/lpc.c
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <rtc.h>
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#include <pci.h>
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#include <asm/acpi.h>
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#include <asm/interrupt.h>
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#include <asm/io.h>
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#include <asm/ioapic.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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#define NMI_OFF 0
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#define ENABLE_ACPI_MODE_IN_COREBOOT 0
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#define TEST_SMM_FLASH_LOCKDOWN 0
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static int pch_enable_apic(pci_dev_t dev)
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{
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u32 reg32;
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int i;
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/* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
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x86_pci_write_config8(dev, ACPI_CNTL, 0x80);
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writel(0, IO_APIC_INDEX);
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writel(1 << 25, IO_APIC_DATA);
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/* affirm full set of redirection table entries ("write once") */
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writel(1, IO_APIC_INDEX);
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reg32 = readl(IO_APIC_DATA);
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writel(1, IO_APIC_INDEX);
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writel(reg32, IO_APIC_DATA);
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writel(0, IO_APIC_INDEX);
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reg32 = readl(IO_APIC_DATA);
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debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f);
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if (reg32 != (1 << 25)) {
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printf("APIC Error - cannot write to registers\n");
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return -EPERM;
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}
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debug("Dumping IOAPIC registers\n");
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for (i = 0; i < 3; i++) {
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writel(i, IO_APIC_INDEX);
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debug(" reg 0x%04x:", i);
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reg32 = readl(IO_APIC_DATA);
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debug(" 0x%08x\n", reg32);
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}
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/* Select Boot Configuration register. */
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writel(3, IO_APIC_INDEX);
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/* Use Processor System Bus to deliver interrupts. */
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writel(1, IO_APIC_DATA);
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return 0;
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}
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static void pch_enable_serial_irqs(pci_dev_t dev)
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{
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u32 value;
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/* Set packet length and toggle silent mode bit for one frame. */
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value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
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#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
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x86_pci_write_config8(dev, SERIRQ_CNTL, value);
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#else
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x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
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#endif
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}
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static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
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{
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uint8_t route[8], *ptr;
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if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route,
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sizeof(route)))
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return -EINVAL;
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ptr = route;
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x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++);
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/*
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* TODO(sjg@chromium.org): U-Boot does not set up the interrupts
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* here. It's unclear if it is needed
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*/
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return 0;
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}
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static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
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{
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u8 route[16];
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u32 reg;
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int gpi;
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if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
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sizeof(route)))
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return -EINVAL;
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for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
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reg |= route[gpi] << (gpi * 2);
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x86_pci_write_config32(dev, 0xb8, reg);
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return 0;
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}
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static int pch_power_options(const void *blob, int node, pci_dev_t dev)
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{
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u8 reg8;
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u16 reg16, pmbase;
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u32 reg32;
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const char *state;
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int pwr_on;
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int nmi_option;
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int ret;
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/*
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* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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* 1 == S5 Soft Off
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*
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* If the option is not existent (Laptops), use Kconfig setting.
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* TODO(sjg@chromium.org): Make this configurable
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*/
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pwr_on = MAINBOARD_POWER_ON;
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reg16 = x86_pci_read_config16(dev, GEN_PMCON_3);
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reg16 &= 0xfffe;
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switch (pwr_on) {
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case MAINBOARD_POWER_OFF:
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reg16 |= 1;
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state = "off";
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break;
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case MAINBOARD_POWER_ON:
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reg16 &= ~1;
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state = "on";
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break;
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case MAINBOARD_POWER_KEEP:
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reg16 &= ~1;
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state = "state keep";
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break;
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default:
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state = "undefined";
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}
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reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
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reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
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reg16 &= ~(1 << 10);
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reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
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reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
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x86_pci_write_config16(dev, GEN_PMCON_3, reg16);
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debug("Set power %s after power failure.\n", state);
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/* Set up NMI on errors. */
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reg8 = inb(0x61);
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reg8 &= 0x0f; /* Higher Nibble must be 0 */
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reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
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reg8 |= (1 << 2); /* PCI SERR# Disable for now */
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outb(reg8, 0x61);
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reg8 = inb(0x70);
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/* TODO(sjg@chromium.org): Make this configurable */
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nmi_option = NMI_OFF;
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if (nmi_option) {
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debug("NMI sources enabled.\n");
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reg8 &= ~(1 << 7); /* Set NMI. */
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} else {
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debug("NMI sources disabled.\n");
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/* Can't mask NMI from PCI-E and NMI_NOW */
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reg8 |= (1 << 7);
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}
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outb(reg8, 0x70);
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/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
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reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
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reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
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reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
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reg16 |= (3 << 0); /* Periodic SMI every 8s */
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#endif
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x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
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/* Set the board's GPI routing. */
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ret = pch_gpi_routing(blob, node, dev);
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if (ret)
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return ret;
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pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe;
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writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
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"intel,gpe0-enable", 0));
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writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
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"intel,alt-gp-smi-enable", 0));
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/* Set up power management block and determine sleep mode */
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reg32 = inl(pmbase + 0x04); /* PM1_CNT */
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reg32 &= ~(7 << 10); /* SLP_TYP */
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reg32 |= (1 << 0); /* SCI_EN */
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outl(reg32, pmbase + 0x04);
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/* Clear magic status bits to prevent unexpected wake */
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setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
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clrbits_le32(RCB_REG(0x3f02), 0xf);
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return 0;
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}
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static void pch_rtc_init(pci_dev_t dev)
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{
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int rtc_failed;
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u8 reg8;
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reg8 = x86_pci_read_config8(dev, GEN_PMCON_3);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~RTC_BATTERY_DEAD;
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x86_pci_write_config8(dev, GEN_PMCON_3, reg8);
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}
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debug("rtc_failed = 0x%x\n", rtc_failed);
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#if CONFIG_HAVE_ACPI_RESUME
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/* Avoid clearing pending interrupts and resetting the RTC control
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* register in the resume path because the Linux kernel relies on
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* this to know if it should restart the RTC timerqueue if the wake
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* was due to the RTC alarm.
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*/
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if (acpi_get_slp_type() == 3)
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return;
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#endif
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/* TODO: Handle power failure */
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if (rtc_failed)
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printf("RTC power failed\n");
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rtc_init();
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}
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/* CougarPoint PCH Power Management init */
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static void cpt_pm_init(pci_dev_t dev)
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{
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debug("CougarPoint PM init\n");
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x86_pci_write_config8(dev, 0xa9, 0x47);
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setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
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setbits_le32(RCB_REG(0x228c), 1 << 0);
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setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
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setbits_le32(RCB_REG(0x0900), 1 << 14);
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writel(0xc0388400, RCB_REG(0x2304));
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setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
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setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
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clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
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writel(0x050f0000, RCB_REG(0x3318));
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writel(0x04000000, RCB_REG(0x3324));
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setbits_le32(RCB_REG(0x3340), 0xfffff);
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setbits_le32(RCB_REG(0x3344), 1 << 1);
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writel(0x0001c000, RCB_REG(0x3360));
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writel(0x00061100, RCB_REG(0x3368));
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writel(0x7f8fdfff, RCB_REG(0x3378));
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writel(0x000003fc, RCB_REG(0x337c));
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writel(0x00001000, RCB_REG(0x3388));
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writel(0x0001c000, RCB_REG(0x3390));
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writel(0x00000800, RCB_REG(0x33a0));
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writel(0x00001000, RCB_REG(0x33b0));
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writel(0x00093900, RCB_REG(0x33c0));
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writel(0x24653002, RCB_REG(0x33cc));
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writel(0x062108fe, RCB_REG(0x33d0));
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clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
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writel(0x01010000, RCB_REG(0x3a28));
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writel(0x01010404, RCB_REG(0x3a2c));
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writel(0x01041041, RCB_REG(0x3a80));
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clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
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setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
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setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */
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writel(0x00000001, RCB_REG(0x3a6c));
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clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
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clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
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writel(0, RCB_REG(0x33c8));
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setbits_le32(RCB_REG(0x21b0), 0xf);
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}
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/* PantherPoint PCH Power Management init */
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static void ppt_pm_init(pci_dev_t dev)
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{
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debug("PantherPoint PM init\n");
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x86_pci_write_config8(dev, 0xa9, 0x47);
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setbits_le32(RCB_REG(0x2238), 1 << 0);
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setbits_le32(RCB_REG(0x228c), 1 << 0);
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setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
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setbits_le16(RCB_REG(0x0900), 1 << 14);
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writel(0xc03b8400, RCB_REG(0x2304));
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setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
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setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
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clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);
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writel(0x054f0000, RCB_REG(0x3318));
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writel(0x04000000, RCB_REG(0x3324));
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setbits_le32(RCB_REG(0x3340), 0xfffff);
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setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));
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writel(0x0001c000, RCB_REG(0x3360));
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writel(0x00061100, RCB_REG(0x3368));
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writel(0x7f8fdfff, RCB_REG(0x3378));
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writel(0x000003fd, RCB_REG(0x337c));
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writel(0x00001000, RCB_REG(0x3388));
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writel(0x0001c000, RCB_REG(0x3390));
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writel(0x00000800, RCB_REG(0x33a0));
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writel(0x00001000, RCB_REG(0x33b0));
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writel(0x00093900, RCB_REG(0x33c0));
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writel(0x24653002, RCB_REG(0x33cc));
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writel(0x067388fe, RCB_REG(0x33d0));
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clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
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writel(0x01010000, RCB_REG(0x3a28));
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writel(0x01010404, RCB_REG(0x3a2c));
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writel(0x01040000, RCB_REG(0x3a80));
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clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
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/* SATA 2/3 disabled */
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setbits_le32(RCB_REG(0x3a84), 1 << 24);
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/* SATA 4/5 disabled */
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setbits_le32(RCB_REG(0x3a88), 1 << 0);
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writel(0x00000001, RCB_REG(0x3a6c));
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clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);
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clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
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setbits_le32(RCB_REG(0x33a4), (1 << 0));
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writel(0, RCB_REG(0x33c8));
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setbits_le32(RCB_REG(0x21b0), 0xf);
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}
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static void enable_hpet(void)
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{
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/* Move HPET to default address 0xfed00000 and enable it */
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clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
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}
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static void enable_clock_gating(pci_dev_t dev)
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{
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u32 reg32;
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u16 reg16;
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setbits_le32(RCB_REG(0x2234), 0xf);
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reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
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reg16 |= (1 << 2) | (1 << 11);
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x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
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pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
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pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
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pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
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pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
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reg32 = readl(RCB_REG(CG));
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reg32 |= (1 << 31);
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reg32 |= (1 << 29) | (1 << 28);
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reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
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reg32 |= (1 << 16);
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reg32 |= (1 << 17);
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reg32 |= (1 << 18);
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reg32 |= (1 << 22);
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reg32 |= (1 << 23);
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reg32 &= ~(1 << 20);
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reg32 |= (1 << 19);
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reg32 |= (1 << 0);
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reg32 |= (0xf << 1);
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writel(reg32, RCB_REG(CG));
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setbits_le32(RCB_REG(0x38c0), 0x7);
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setbits_le32(RCB_REG(0x36d4), 0x6680c004);
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setbits_le32(RCB_REG(0x3564), 0x3);
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}
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#if CONFIG_HAVE_SMI_HANDLER
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static void pch_lock_smm(pci_dev_t dev)
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{
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#if TEST_SMM_FLASH_LOCKDOWN
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u8 reg8;
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#endif
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if (acpi_slp_type != 3) {
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#if ENABLE_ACPI_MODE_IN_COREBOOT
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debug("Enabling ACPI via APMC:\n");
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outb(0xe1, 0xb2); /* Enable ACPI mode */
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debug("done.\n");
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#else
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debug("Disabling ACPI via APMC:\n");
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outb(0x1e, 0xb2); /* Disable ACPI mode */
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debug("done.\n");
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#endif
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}
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/* Don't allow evil boot loaders, kernels, or
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* userspace applications to deceive us:
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*/
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smm_lock();
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#if TEST_SMM_FLASH_LOCKDOWN
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/* Now try this: */
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debug("Locking BIOS to RO... ");
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reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
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(reg8 & 1) ? "rw" : "ro");
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reg8 &= ~(1 << 0); /* clear BIOSWE */
|
|
x86_pci_write_config8(dev, 0xdc, reg8);
|
|
reg8 |= (1 << 1); /* set BLE */
|
|
x86_pci_write_config8(dev, 0xdc, reg8);
|
|
debug("ok.\n");
|
|
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
|
debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
|
|
(reg8 & 1) ? "rw" : "ro");
|
|
|
|
debug("Writing:\n");
|
|
writeb(0, 0xfff00000);
|
|
debug("Testing:\n");
|
|
reg8 |= (1 << 0); /* set BIOSWE */
|
|
x86_pci_write_config8(dev, 0xdc, reg8);
|
|
|
|
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
|
debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
|
|
(reg8 & 1) ? "rw" : "ro");
|
|
debug("Done.\n");
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
static void pch_disable_smm_only_flashing(pci_dev_t dev)
|
|
{
|
|
u8 reg8;
|
|
|
|
debug("Enabling BIOS updates outside of SMM... ");
|
|
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
|
reg8 &= ~(1 << 5);
|
|
x86_pci_write_config8(dev, 0xdc, reg8);
|
|
}
|
|
|
|
static void pch_fixups(pci_dev_t dev)
|
|
{
|
|
u8 gen_pmcon_2;
|
|
|
|
/* Indicate DRAM init done for MRC S3 to know it can resume */
|
|
gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2);
|
|
gen_pmcon_2 |= (1 << 7);
|
|
x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
|
|
|
|
/* Enable DMI ASPM in the PCH */
|
|
clrbits_le32(RCB_REG(0x2304), 1 << 10);
|
|
setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
|
|
setbits_le32(RCB_REG(0x21a8), 0x3);
|
|
}
|
|
|
|
int lpc_early_init(const void *blob, int node, pci_dev_t dev)
|
|
{
|
|
struct reg_info {
|
|
u32 base;
|
|
u32 size;
|
|
} values[4], *ptr;
|
|
int count;
|
|
int i;
|
|
|
|
count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
|
|
(u32 *)values, sizeof(values) / sizeof(u32));
|
|
if (count < 0)
|
|
return -EINVAL;
|
|
|
|
/* Set COM1/COM2 decode range */
|
|
x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010);
|
|
|
|
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
|
|
x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
|
|
GAMEL_LPC_EN | COMA_LPC_EN);
|
|
|
|
/* Write all registers but use 0 if we run out of data */
|
|
count = count * sizeof(u32) / sizeof(values[0]);
|
|
for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
|
|
u32 reg = 0;
|
|
|
|
if (i < count)
|
|
reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
|
|
x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int lpc_init(struct pci_controller *hose, pci_dev_t dev)
|
|
{
|
|
const void *blob = gd->fdt_blob;
|
|
int node;
|
|
|
|
debug("pch: lpc_init\n");
|
|
pci_write_bar32(hose, dev, 0, 0);
|
|
pci_write_bar32(hose, dev, 1, 0xff800000);
|
|
pci_write_bar32(hose, dev, 2, 0xfec00000);
|
|
pci_write_bar32(hose, dev, 3, 0x800);
|
|
pci_write_bar32(hose, dev, 4, 0x900);
|
|
|
|
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
|
|
if (node < 0)
|
|
return -ENOENT;
|
|
|
|
/* Set the value for PCI command register. */
|
|
x86_pci_write_config16(dev, PCI_COMMAND, 0x000f);
|
|
|
|
/* IO APIC initialization. */
|
|
pch_enable_apic(dev);
|
|
|
|
pch_enable_serial_irqs(dev);
|
|
|
|
/* Setup the PIRQ. */
|
|
pch_pirq_init(blob, node, dev);
|
|
|
|
/* Setup power options. */
|
|
pch_power_options(blob, node, dev);
|
|
|
|
/* Initialize power management */
|
|
switch (pch_silicon_type()) {
|
|
case PCH_TYPE_CPT: /* CougarPoint */
|
|
cpt_pm_init(dev);
|
|
break;
|
|
case PCH_TYPE_PPT: /* PantherPoint */
|
|
ppt_pm_init(dev);
|
|
break;
|
|
default:
|
|
printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev),
|
|
PCI_FUNC(dev));
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/* Initialize the real time clock. */
|
|
pch_rtc_init(dev);
|
|
|
|
/* Initialize the High Precision Event Timers, if present. */
|
|
enable_hpet();
|
|
|
|
/* Initialize Clock Gating */
|
|
enable_clock_gating(dev);
|
|
|
|
pch_disable_smm_only_flashing(dev);
|
|
|
|
#if CONFIG_HAVE_SMI_HANDLER
|
|
pch_lock_smm(dev);
|
|
#endif
|
|
|
|
pch_fixups(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void lpc_enable(pci_dev_t dev)
|
|
{
|
|
/* Enable PCH Display Port */
|
|
writew(0x0010, RCB_REG(DISPBDF));
|
|
setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
|
|
}
|
|
|
|
static const struct udevice_id bd82x6x_lpc_ids[] = {
|
|
{ .compatible = "intel,bd82x6x-lpc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
|
|
.name = "lpc",
|
|
.id = UCLASS_LPC,
|
|
.of_match = bd82x6x_lpc_ids,
|
|
};
|
|
|