upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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123 lines
2.2 KiB
123 lines
2.2 KiB
/*
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* From Coreboot
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2012 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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static int pch_revision_id = -1;
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static int pch_type = -1;
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int pch_silicon_revision(void)
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{
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pci_dev_t dev;
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dev = PCH_LPC_DEV;
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if (pch_revision_id < 0)
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pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID);
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return pch_revision_id;
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}
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int pch_silicon_type(void)
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{
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pci_dev_t dev;
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dev = PCH_LPC_DEV;
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if (pch_type < 0)
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pch_type = x86_pci_read_config8(dev, PCI_DEVICE_ID + 1);
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return pch_type;
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}
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int pch_silicon_supported(int type, int rev)
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{
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int cur_type = pch_silicon_type();
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int cur_rev = pch_silicon_revision();
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switch (type) {
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case PCH_TYPE_CPT:
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/* CougarPoint minimum revision */
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if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
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return 1;
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/* PantherPoint any revision */
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if (cur_type == PCH_TYPE_PPT)
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return 1;
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break;
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case PCH_TYPE_PPT:
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/* PantherPoint minimum revision */
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if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
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return 1;
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break;
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}
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return 0;
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}
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#define IOBP_RETRY 1000
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static inline int iobp_poll(void)
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{
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unsigned try = IOBP_RETRY;
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u32 data;
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while (try--) {
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data = readl(RCB_REG(IOBPS));
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if ((data & 1) == 0)
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return 1;
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udelay(10);
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}
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printf("IOBP timeout\n");
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return 0;
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}
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void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
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{
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u32 data;
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/* Set the address */
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writel(address, RCB_REG(IOBPIRI));
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/* READ OPCODE */
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if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
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writel(IOBPS_RW_BX, RCB_REG(IOBPS));
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else
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writel(IOBPS_READ_AX, RCB_REG(IOBPS));
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if (!iobp_poll())
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return;
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/* Read IOBP data */
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data = readl(RCB_REG(IOBPD));
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if (!iobp_poll())
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return;
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/* Check for successful transaction */
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if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
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printf("IOBP read 0x%08x failed\n", address);
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return;
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}
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/* Update the data */
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data &= andvalue;
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data |= orvalue;
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/* WRITE OPCODE */
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if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
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writel(IOBPS_RW_BX, RCB_REG(IOBPS));
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else
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writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
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if (!iobp_poll())
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return;
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/* Write IOBP data */
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writel(data, RCB_REG(IOBPD));
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if (!iobp_poll())
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return;
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}
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