upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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67 lines
1.5 KiB
67 lines
1.5 KiB
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008,2009
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/arch/bd82x6x.h>
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#include <asm/arch/pch.h>
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static int pci_ivybridge_probe(struct udevice *bus)
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{
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struct pci_controller *hose = dev_get_uclass_priv(bus);
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pci_dev_t dev;
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u16 reg16;
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if (!(gd->flags & GD_FLG_RELOC))
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return 0;
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post_code(0x50);
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bd82x6x_init();
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post_code(0x51);
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reg16 = 0xff;
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dev = PCH_DEV;
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reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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x86_pci_write_config16(dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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pci_write_bar32(hose, dev, 0, 0xf0000000);
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post_code(0x52);
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return 0;
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}
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static const struct dm_pci_ops pci_ivybridge_ops = {
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.read_config = pci_x86_read_config,
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.write_config = pci_x86_write_config,
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};
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static const struct udevice_id pci_ivybridge_ids[] = {
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{ .compatible = "intel,pci-ivybridge" },
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{ }
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};
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U_BOOT_DRIVER(pci_ivybridge_drv) = {
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.name = "pci_ivybridge",
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.id = UCLASS_PCI,
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.of_match = pci_ivybridge_ids,
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.ops = &pci_ivybridge_ops,
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.probe = pci_ivybridge_probe,
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};
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