upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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226 lines
6.5 KiB
226 lines
6.5 KiB
/*
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* From Coreboot
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/bd82x6x.h>
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static inline u32 sir_read(pci_dev_t dev, int idx)
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{
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x86_pci_write_config32(dev, SATA_SIRI, idx);
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return x86_pci_read_config32(dev, SATA_SIRD);
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}
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static inline void sir_write(pci_dev_t dev, int idx, u32 value)
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{
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x86_pci_write_config32(dev, SATA_SIRI, idx);
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x86_pci_write_config32(dev, SATA_SIRD, value);
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}
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static void common_sata_init(pci_dev_t dev, unsigned int port_map)
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{
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u32 reg32;
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u16 reg16;
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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x86_pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Port enable */
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reg16 = x86_pci_read_config16(dev, 0x92);
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reg16 &= ~0x3f;
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reg16 |= port_map;
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x86_pci_write_config16(dev, 0x92, reg16);
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/* SATA Initialization register */
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port_map &= 0xff;
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x86_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
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}
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void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
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{
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unsigned int port_map, speed_support, port_tx;
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struct pci_controller *hose = pci_bus_to_hose(0);
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const char *mode;
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u32 reg32;
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u16 reg16;
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debug("SATA: Initializing...\n");
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/* SATA configuration */
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port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
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speed_support = fdtdec_get_int(blob, node,
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"sata_interface_speed_support", 0);
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/* Enable BARs */
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x86_pci_write_config16(dev, PCI_COMMAND, 0x0007);
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mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
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if (!mode || !strcmp(mode, "ahci")) {
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u32 abar;
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debug("SATA: Controller in AHCI mode\n");
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/* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
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x86_pci_write_config8(dev, INTR_LN, 0x0a);
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/* Set timings */
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x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
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/* Sync DMA */
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x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
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x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
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common_sata_init(dev, 0x8000 | port_map);
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/* Initialize AHCI memory-mapped space */
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abar = pci_read_bar32(hose, dev, 5);
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debug("ABAR: %08X\n", abar);
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/* CAP (HBA Capabilities) : enable power management */
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reg32 = readl(abar + 0x00);
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reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */
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reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
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/* Set ISS, if available */
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if (speed_support) {
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reg32 &= ~0x00f00000;
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reg32 |= (speed_support & 0x03) << 20;
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}
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writel(reg32, abar + 0x00);
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/* PI (Ports implemented) */
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writel(port_map, abar + 0x0c);
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(void) readl(abar + 0x0c); /* Read back 1 */
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(void) readl(abar + 0x0c); /* Read back 2 */
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/* CAP2 (HBA Capabilities Extended)*/
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reg32 = readl(abar + 0x24);
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reg32 &= ~0x00000002;
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writel(reg32, abar + 0x24);
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/* VSP (Vendor Specific Register */
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reg32 = readl(abar + 0xa0);
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reg32 &= ~0x00000005;
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writel(reg32, abar + 0xa0);
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} else if (!strcmp(mode, "combined")) {
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debug("SATA: Controller in combined mode\n");
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/* No AHCI: clear AHCI base */
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pci_write_bar32(hose, dev, 5, 0x00000000);
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/* And without AHCI BAR no memory decoding */
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reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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x86_pci_write_config16(dev, PCI_COMMAND, reg16);
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x86_pci_write_config8(dev, 0x09, 0x80);
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/* Set timings */
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x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
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x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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/* Sync DMA */
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x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
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x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
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common_sata_init(dev, port_map);
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} else {
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debug("SATA: Controller in plain-ide mode\n");
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/* No AHCI: clear AHCI base */
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pci_write_bar32(hose, dev, 5, 0x00000000);
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/* And without AHCI BAR no memory decoding */
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reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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x86_pci_write_config16(dev, PCI_COMMAND, reg16);
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/*
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* Native mode capable on both primary and secondary (0xa)
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* OR'ed with enabled (0x50) = 0xf
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*/
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x86_pci_write_config8(dev, 0x09, 0x8f);
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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x86_pci_write_config8(dev, INTR_LN, 0xff);
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/* Set timings */
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x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_SITRE | IDE_ISP_3_CLOCKS |
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IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
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/* Sync DMA */
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x86_pci_write_config16(dev, IDE_SDMA_CNT,
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IDE_SSDE0 | IDE_PSDE0);
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x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
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common_sata_init(dev, port_map);
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}
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/* Set Gen3 Transmitter settings if needed */
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port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
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if (port_tx)
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pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx);
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port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
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if (port_tx)
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pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx);
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/* Additional Programming Requirements */
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sir_write(dev, 0x04, 0x00001600);
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sir_write(dev, 0x28, 0xa0000033);
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reg32 = sir_read(dev, 0x54);
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reg32 &= 0xff000000;
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reg32 |= 0x5555aa;
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sir_write(dev, 0x54, reg32);
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sir_write(dev, 0x64, 0xcccc8484);
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reg32 = sir_read(dev, 0x68);
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reg32 &= 0xffff0000;
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reg32 |= 0xcccc;
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sir_write(dev, 0x68, reg32);
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reg32 = sir_read(dev, 0x78);
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reg32 &= 0x0000ffff;
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reg32 |= 0x88880000;
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sir_write(dev, 0x78, reg32);
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sir_write(dev, 0x84, 0x001c7000);
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sir_write(dev, 0x88, 0x88338822);
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sir_write(dev, 0xa0, 0x001c7000);
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sir_write(dev, 0xc4, 0x0c0c0c0c);
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sir_write(dev, 0xc8, 0x0c0c0c0c);
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sir_write(dev, 0xd4, 0x10000000);
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pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
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pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
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}
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void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
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{
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unsigned port_map;
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const char *mode;
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u16 map = 0;
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/*
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* Set SATA controller mode early so the resource allocator can
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* properly assign IO/Memory resources for the controller.
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*/
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mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
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if (mode && !strcmp(mode, "ahci"))
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map = 0x0060;
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port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
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map |= (port_map ^ 0x3f) << 8;
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x86_pci_write_config16(dev, 0x90, map);
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}
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